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AHgh+RomsHghT+TOjNTNQEiKbRFD7ypyn3XDx8VE4O4uT2wZNYEAWNfn++9VQvAIehUaw5Hi3aJ/COxQW56pyOs=@vger.kernel.org X-Gm-Message-State: AOJu0Yz6KF4vXARk8osYIDkVKjp6UfldcLd9shZt+1J9NWBcCocB+uCM TVxyqopPT9vACNRrGvauST8XunsyMhkow/EpU7XdArdnez6EVBXBzKqTlR4JGah2GJBZ/IL+ozu nS7h2trpM/YRjbFoQN/7FoJ5BLIW3s/UgZJFsGE+jhg== X-Gm-Gg: AfdE7clhVLzITRmG6hSIzzzA3pkpg/19faEZ79yd/F5xslN70xWBf8q00MXATg/Q8jW ZhZNEx3z4AR0rX9J0xCDS+ip3Vpe3hheXY9Mm4IlXjygreqKmxz4JdT0wPjvWflSsr1Ojlq98a8 ADEm9bgOYXKw1PJY/dTDstECeWfEEOELJ+VV4sbMtN3oEZW3iQtbxM1r00hPU0RR0fcnCzQKt40 RD+N0aJSwNnvjTDg4qL0QL6sKnSMmv7dvcubRvpwyix2KoO0CSqENLpqnJDQ6PztSQYDfnq2TFv s8EFv2HAANAS+5T77lpn3ujS X-Received: by 2002:a05:620a:2b95:b0:92f:196:20a3 with SMTP id af79cd13be357-930b41f8197mr365180085a.66.1784308787556; Fri, 17 Jul 2026 10:19:47 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20260715132009.10634-1-luxu.kernel@bytedance.com> <20260715132009.10634-2-luxu.kernel@bytedance.com> In-Reply-To: From: Xu Lu Date: Sat, 18 Jul 2026 01:19:35 +0800 X-Gm-Features: AUfX_myg-L39l6GlUwXOVLYk6M8taEnjtEURrAIcWUkhR8pG-Uaqkgrm7iKCki4 Message-ID: Subject: Re: [External] Re: [PATCH v2 1/3] riscv: mm: Use ASID in update_mmu_cache() To: Klara Modin , Paul Walmsley Cc: Paul Walmsley , palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks, Klara. Thanks, Paul. Best regards, Xu Lu On Sat, Jul 18, 2026 at 1:15=E2=80=AFAM Klara Modin = wrote: > > On 2026-07-18 00:57:06 +0800, Xu Lu wrote: > > Hi Paul, > > > > A gentle ping. > > > > I have no idea what I can do regarding linux-next. Could you please > > help revert the patch from version 1 and cherry-pick all the patches > > from version 2 instead? Or what can I do for this? > > Paul has updated the for-next branch at > git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git so it should > sort itself out to either today's or monday's next version (depending on > if the tree has already been pulled or not). Even if it is not pulled > until monday I think it will be fine, this is what linux-next is for > after all. > > Regards, > Klara Modin > > > > > Best regards, > > Xu Lu > > > > On Fri, Jul 17, 2026 at 10:11=E2=80=AFAM Xu Lu wrote: > > > > > > Hi Paul, > > > > > > Klara found that linux-next cherry-picks the new version of patch 2 > > > while picking the old version of patch 1, which leads to an > > > uninitialized asid. Could you please help correct this? > > > > > > Best regards, > > > Xu Lu > > > > > > On Fri, Jul 17, 2026 at 12:25=E2=80=AFAM Klara Modin wrote: > > > > > > > > Hi, > > > > > > > > On 2026-07-15 21:20:07 +0800, Xu Lu wrote: > > > > > Only flush TLB entries for the specified mm in update_mmu_cache_r= ange(). > > > > > > > > > > Signed-off-by: Xu Lu > > > > > --- > > > > > arch/riscv/include/asm/pgtable.h | 4 +++- > > > > > arch/riscv/include/asm/tlbflush.h | 5 +++++ > > > > > arch/riscv/mm/tlbflush.c | 5 ----- > > > > > 3 files changed, 8 insertions(+), 6 deletions(-) > > > > > > > > > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/includ= e/asm/pgtable.h > > > > > index 5d5756bda82e..9926556099ae 100644 > > > > > --- a/arch/riscv/include/asm/pgtable.h > > > > > +++ b/arch/riscv/include/asm/pgtable.h > > > > > @@ -568,6 +568,8 @@ static inline void update_mmu_cache_range(str= uct vm_fault *vmf, > > > > > struct vm_area_struct *vma, unsigned long address, > > > > > pte_t *ptep, unsigned int nr) > > > > > { > > > > > + unsigned long asid =3D get_mm_asid(vma->vm_mm); > > > > > + > > > > > > > > It seems the old version of this patch is still used (at least in > > > > next-202650716, 15ce1d7c4ddfe0dff00fcaee4ccaeef3efbc62c6), which me= ans > > > > asid is not initialised here. We instead have: > > > > > > > > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/= asm/pgtable.h > > > > index 5d5756bda82e..755495a542cc 100644 > > > > --- a/arch/riscv/include/asm/pgtable.h > > > > +++ b/arch/riscv/include/asm/pgtable.h > > > > @@ -568,6 +568,8 @@ static inline void update_mmu_cache_range(struc= t vm_fault *vmf, > > > > struct vm_area_struct *vma, unsigned long address, > > > > pte_t *ptep, unsigned int nr) > > > > { > > > > + unsigned long asid; > > > > + > > > > /* > > > > * Svvptc guarantees that the new valid pte will be visible= within > > > > * a bounded timeframe, so when the uarch does not cache in= valid > > > > @@ -583,10 +585,11 @@ static inline void update_mmu_cache_range(str= uct vm_fault *vmf, > > > > * Relying on flush_tlb_fix_spurious_fault would suffice, b= ut > > > > * the extra traps reduce performance. So, eagerly SFENCE.= VMA. > > > > */ > > > > + asid =3D get_mm_asid(vma->vm_mm); > > > > while (nr--) > > > > - local_flush_tlb_page(address + nr * PAGE_SIZE); > > > > - > > > > + local_flush_tlb_page_asid(address + nr * PAGE_SIZE,= asid); > > > > } > > > > + > > > > #define update_mmu_cache(vma, addr, ptep) \ > > > > update_mmu_cache_range(NULL, vma, addr, ptep, 1) > > > > > > > > > > > > This means that patch 2 of this series will use the uninitialised a= sid > > > > for local_svinval_vma() and I get the same behaviour as before (han= g on > > > > initramfs). If I revert the two patches of this series which are in= next > > > > and apply this again it's fine. > > > > > > > > Regards, > > > > Klara Modin > > ...