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AJvYcCVgas/7uOC70VJZeljLE4Ph4OYqY/+U8wTk94tSzySbNUDhAYza+RvURF56rckyCWWo2aotQCKEOOyekkY=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7IDhTv7xbVXXCbn6Ym1ly6/3/o+E+4YKpz6xmzhso23IPOEK1 jGj15RMZuVRpl6zkbcKjQ7NzHu8VScvH9Fq4uwPWoeVwNS8JM3VNn3ICRBXdV9Hslh3RoXkj+N+ IaC9hFpBZmhvjG/X5hIKdENOp5CQLRXXHkyMLHg== X-Gm-Gg: ASbGnctn/7tEAaV5z61q0OgQQcBPntJBptZ2zsRh7kqJ6i7/gzp9ZVuQqHaHAoJEiDX GVr2ClMV4/Jz/5BwY0hPDZdP/zMBa+M/+cVUVclFLX4oNo7B3GdMAlRKkGL0RfYvT X-Google-Smtp-Source: AGHT+IFRYQDgGAlxpuyP6F5Z7RaISZNaZ2D+OJF5GWa9/zTfvuVdKObwEF+LucM85N/3Px+2rORXWhlhlMLAJb/FB3o= X-Received: by 2002:a17:90b:3d4e:b0:2ee:7870:8835 with SMTP id 98e67ed59e1d1-2f782d97f47mr67401510a91.33.1737995880453; Mon, 27 Jan 2025 08:38:00 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250127093846.98625-1-luxu.kernel@bytedance.com> In-Reply-To: From: Xu Lu Date: Tue, 28 Jan 2025 00:37:49 +0800 X-Gm-Features: AWEUYZmDP1k6aWrWrlOgQTMC7s5NBiXPrHUqeHPlh8HrZuvgn9WCfnSSwa7uIx4 Message-ID: Subject: Re: [External] Re: [PATCH RESEND] irqchip: riscv: Order normal writes and IPI writes To: Arnd Bergmann Cc: Thomas Gleixner , Anup Patel , Charlie Jenkins , Paul Walmsley , Palmer Dabbelt , lihangjing@bytedance.com, Xie Yongji , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jan 28, 2025 at 12:23=E2=80=AFAM Arnd Bergmann wrot= e: > > On Mon, Jan 27, 2025, at 10:38, Xu Lu wrote: > > RISC-V distinguishes between normal memory accesses and device I/O and > > uses FENCE instruction to order them as viewed by othe RISC-V harts and > > external devices or coprocessors. The FENCE instruction can order any > > combination of device input(I), device output(O), memory reads(R) and > > memory writes(W). For example, 'fence w, o' can be used to ensure all > > memory writes from instructions preceding the FENCE instruction appear > > earlier in the global memory order than device output writes from > > instructions after the FENCE instruction. > > There is nothing risc-v specific in here really, it's just a bug > in the driver: writel() means access the mmio register with appropriate > barriers, while writel_relaxed() is a special case that should > only ever be used if a particular function is sensitive to > performance and never needs to be serialized. > > > diff --git a/drivers/irqchip/irq-thead-c900-aclint-sswi.c > > b/drivers/irqchip/irq-thead-c900-aclint-sswi.c > > index b0e366ade427..8ff6e7a1363b 100644 > > --- a/drivers/irqchip/irq-thead-c900-aclint-sswi.c > > +++ b/drivers/irqchip/irq-thead-c900-aclint-sswi.c > > @@ -31,7 +31,7 @@ static DEFINE_PER_CPU(void __iomem *, sswi_cpu_regs); > > > > static void thead_aclint_sswi_ipi_send(unsigned int cpu) > > { > > - writel_relaxed(0x1, per_cpu(sswi_cpu_regs, cpu)); > > + writel(0x1, per_cpu(sswi_cpu_regs, cpu)); > > } > > > > static void thead_aclint_sswi_ipi_clear(void) > > -- > > thead_aclint_sswi_ipi_clear() seems to have the same bug, > it also uses the _relaxed() version for no apparent reason. Hi Arnd, There seems no need to modify thead_aclint_sswi_ipi_clear() as it only clears pending IPI on current hart. No other harts require to see strict order between preceding memory writes and this ACLINT MMIO write. Please correct me if I missed anything. Thanks, Xu Lu > > Arnd