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([2402:7500:4ce:aeef:99fc:78aa:eebe:b7e0]) by smtp.gmail.com with ESMTPSA id w13-20020a170902e88d00b001c627413e87sm4301587plg.290.2023.11.09.20.06.12 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Nov 2023 20:06:16 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.7\)) Subject: Re: [PATCH 06/12] RISC-V: crypto: add accelerated AES-CBC/CTR/ECB/XTS implementations From: Jerry Shih In-Reply-To: <20231109080549.GC1245@sol.localdomain> Date: Fri, 10 Nov 2023 12:06:10 +0800 Cc: Paul Walmsley , palmer@dabbelt.com, Albert Ou , herbert@gondor.apana.org.au, davem@davemloft.net, andy.chiu@sifive.com, greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@kernel.org, bjorn@rivosinc.com, heiko@sntech.de, ardb@kernel.org, phoebe.chen@sifive.com, hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20231025183644.8735-1-jerry.shih@sifive.com> <20231025183644.8735-7-jerry.shih@sifive.com> <20231109080549.GC1245@sol.localdomain> To: Eric Biggers X-Mailer: Apple Mail (2.3445.9.7) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Nov 9, 2023, at 16:05, Eric Biggers wrote: > On Thu, Oct 26, 2023 at 02:36:38AM +0800, Jerry Shih wrote: >> +# prepare input data(v24), iv(v28), bit-reversed-iv(v16), = bit-reversed-iv-multiplier(v20) >> +sub init_first_round { >> .... >> + # Prepare GF(2^128) multiplier [1, x, x^2, x^3, ...] in v8. >> + slli $T0, $LEN32, 2 >> + @{[vsetvli "zero", $T0, "e32", "m1", "ta", "ma"]} >> + # v2: [`1`, `1`, `1`, `1`, ...] >> + @{[vmv_v_i $V2, 1]} >> + # v3: [`0`, `1`, `2`, `3`, ...] >> + @{[vid_v $V3]} >> + @{[vsetvli "zero", $T0, "e64", "m2", "ta", "ma"]} >> + # v4: [`1`, 0, `1`, 0, `1`, 0, `1`, 0, ...] >> + @{[vzext_vf2 $V4, $V2]} >> + # v6: [`0`, 0, `1`, 0, `2`, 0, `3`, 0, ...] >> + @{[vzext_vf2 $V6, $V3]} >> + slli $T0, $LEN32, 1 >> + @{[vsetvli "zero", $T0, "e32", "m2", "ta", "ma"]} >> + # v8: [1<<0=3D1, 0, 0, 0, 1<<1=3Dx, 0, 0, 0, 1<<2=3Dx^2, 0, 0, = 0, ...] >> + @{[vwsll_vv $V8, $V4, $V6]} >=20 > This code assumes that '1 << i' fits in 64 bits, for 0 <=3D i < vl. >=20 > I think that works out to an implicit assumption that VLEN <=3D 2048. = I.e., > AES-XTS encryption/decryption would produce the wrong result on RISC-V > implementations with VLEN > 2048. >=20 > Perhaps it should be explicitly checked that VLEN <=3D 2048? >=20 > - Eric Yes, we could just have the simple checking like: riscv_vector_vlen() >=3D 128 || riscv_vector_vlen() <=3D2048 We could also truncate the VL inside for VLEN>2048 case. Let me think more about these two approaches.=20 -Jerry=