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charset="us-ascii" Content-ID: <5847AA4CB0906E4C9C029576C8B6D279@prod.exchangelabs.com> Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amperecomputing.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL1PR01MB7649.prod.exchangelabs.com X-MS-Exchange-CrossTenant-Network-Message-Id: 048bbc53-5374-4201-10ea-08ddc3d3dc9a X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jul 2025 19:14:46.2872 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3bc2b170-fd94-476d-b0ce-4229bdc904a7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9q8gkIRnMf7541viDeUwkdKa0MECqAYmgoXBixB7bDuW8MeYRGZlIKHYhtnJmdzCMsp5xKnQmkWBf+KhCHBfOOfySGgehUqbFEymHZqa4Do= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR01MB6188 This patch-set tackles a significant task placement imbalance encountered u= nder restricted CPU affinity, particularly on Ampere Altra systems. Our per= formance tests reveal that the first patch demonstrably improves task place= ment by 20-30% in scenarios where the number of threads increasingly outnum= bers the available cores. However, the second patch unexpectedly introduces= regressions when tested against higher thread count scenarios, requiring f= urther investigation. In light of these findings and the potential regression, the following ques= tions arise: Q. Has the regression been investigated to determine if it is specific to = two-level scheduling domains or manifests more broadly? Q. Were function-level latencies profiled to pinpoint the exact source of = the regression within the code path introduced by the second patch? Q. How do these patches influence performance and task placement on system= s with linear topologies, and do they exhibit more consistent behavior in t= hose configurations? - Shubhang=