From: "H. Peter Anvin" <hpa@zytor.com>
To: Arnd Bergmann <arnd@arndb.de>, Arnd Bergmann <arnd@kernel.org>,
Ingo Molnar <mingo@redhat.com>
Cc: Richard Weinberger <richard@nod.at>,
Anton Ivanov <anton.ivanov@cambridgegreys.com>,
Johannes Berg <johannes@sipsolutions.net>,
Thomas Gleixner <tglx@kernel.org>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will@kernel.org>, Boqun Feng <boqun@kernel.org>,
Gary Guo <gary@garyguo.net>, Yury Norov <yury.norov@gmail.com>,
Rasmus Villemoes <linux@rasmusvillemoes.dk>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Alexander Usyskin <alexander.usyskin@intel.com>,
Anthony L Nguyen <anthony.l.nguyen@intel.com>,
Przemek Kitszel <przemyslaw.kitszel@intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org,
linux-um@lists.infradead.org
Subject: Re: [PATCH 7/7] x86: simplify 32-bit instruction set selection
Date: Mon, 09 Nov 2026 10:32:04 -0800 [thread overview]
Message-ID: <D58976E3-E2A3-4577-BC64-5845CF4F82C6@zytor.com> (raw)
In-Reply-To: <eaeec453-892d-4ddb-9d42-0510db8b9c88@app.fastmail.com>
On November 5, 2026 2:01:40 PM PST, Arnd Bergmann <arnd@arndb.de> wrote:
>On Thu, Nov 5, 2026, at 21:17, H. Peter Anvin wrote:
>> On November 5, 2026 8:34:38 AM PST, Arnd Bergmann <arnd@kernel.org> wrote:
>>>From: Arnd Bergmann <arnd@arndb.de>
>>>
>>>The -march= compiler flags select both instruction set and tuning for
>>>a particular CPU, which works well when building a kernel that can only
>>>run on this one type, but has some counterintuitive effects because it
>>>is not always clear which models are compatible.
>>>
>>>E.g. building for Geode LX results in a kernel that can work on all on
>>>all 686-class CPUs but crashes on CPUs without the CMOV instructions.
>>>Building a kernel for 686 could work on Geode LX and Crusoe but fails
>>>because of the CPU generation check that detects these as 585-class.
>...
>>
>> Crusoe (TM3xxx/TM5xxx) do have a handful of compiler/user space visible
>> items that are missing from i686, as I recall notably the long nop
>> instructions and *possibly* fcomi (I *think* we caught that one, but
>> I'm not 100% sure.)
>>
>> As a result, it reports correctly as family 5.
>
>I don't know about fcomi, but the P6 long NOP hasn't been used
>in 32-bit kernels since your 2008 commit 14469a8dd236 ("x86:
>disable static NOPLs on 32 bits"). From that point, I believe
>we effectively treated Geode LX and Crusoe as 686-compatible.
>
>binutils apparently uses the same definition and emits long
>nops for -march=pentiumpro but not for -march=i686 in modern
>versions.
>
>You are of course correct that this remains inconsistent:
>a kernel with CONFIG_MCRUSOE is still built with -march=i686
>and CONFIG_X86_MINIMUM_CPU_FAMILY=5, so it will fail to run
>on 586-class CPUs without CMOV.
>
>I'll fold in this patch to make a MCRUSOE kernel actually compatible
>with all i586-class CPUs, unless you have a better idea:
>
>diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu
>index 1735a5f95d33..9a3a1b1c2452 100644
>--- a/arch/x86/Makefile_32.cpu
>+++ b/arch/x86/Makefile_32.cpu
>@@ -21,7 +21,7 @@ cflags-$(CONFIG_MK6) += -march=i586 $(call tune,k6)
> # Please note, that patches that add -march=athlon-xp and friends are pointless.
> # They make zero difference whatsosever to performance at this time.
> cflags-$(CONFIG_MK7) += -march=i686 $(call tune,athlon)
>-cflags-$(CONFIG_MCRUSOE) += -march=i686 $(align)
>+cflags-$(CONFIG_MCRUSOE) += -march=i586 $(call tune,i686) $(align)
> cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) $(align)
> cflags-$(CONFIG_MCYRIXIII) += -march=i586 $(call tune,i486) $(align)
> cflags-$(CONFIG_MVIAC3_2) += -march=i686
>
> Arnd
Yeah, the problem isn't the kernel, but user space.
prev parent reply other threads:[~2026-11-09 18:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
2026-11-05 16:34 ` [PATCH 1/7] x86: remove AMD Élan remnants Arnd Bergmann
2026-11-05 16:34 ` [PATCH 2/7] x86: make TSC usage unconditional Arnd Bergmann
2026-11-05 16:34 ` [PATCH 3/7] x86: make CX8 " Arnd Bergmann
2026-11-05 22:30 ` Uros Bizjak
2026-11-09 10:20 ` Arnd Bergmann
2026-11-06 2:29 ` kernel test robot
2026-11-06 15:43 ` David Gow
2026-11-08 20:30 ` David Laight
2026-11-09 10:24 ` Arnd Bergmann
2026-11-05 16:34 ` [PATCH 4/7] x86: require minimum 64 byte cache lines Arnd Bergmann
2026-11-05 16:34 ` [PATCH 5/7] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
2026-11-05 16:34 ` [PATCH 6/7] x86: remove dependencies on per-CPU options Arnd Bergmann
2026-11-05 16:34 ` [PATCH 7/7] x86: simplify 32-bit instruction set selection Arnd Bergmann
2026-11-05 20:17 ` H. Peter Anvin
2026-11-05 22:01 ` Arnd Bergmann
2026-11-09 18:32 ` H. Peter Anvin [this message]
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