From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753812AbcFTKat (ORCPT ); Mon, 20 Jun 2016 06:30:49 -0400 Received: from mga02.intel.com ([134.134.136.20]:38847 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752738AbcFTKam convert rfc822-to-8bit (ORCPT ); Mon, 20 Jun 2016 06:30:42 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,497,1459839600"; d="scan'208";a="991283211" From: "Odzioba, Lukasz" To: Peter Zijlstra CC: "linux-kernel@vger.kernel.org" , "x86@kernel.org" , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "ak@linux.intel.com" , "Liang, Kan" , "akpm@linux-foundation.org" , "eranian@google.com" , "acme@kernel.org" , "alexander.shishkin@linux.intel.com" , "bp@suse.de" , "Anaczkowski, Lukasz" Subject: RE: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing Thread-Topic: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing Thread-Index: AQHRwTqrE69m57LPLUuinULhCEnaQZ/fECsAgBMo30A= Date: Mon, 20 Jun 2016 10:26:30 +0000 Message-ID: References: <1465358536-21544-1-git-send-email-lukasz.odzioba@intel.com> <20160608064800.GN30154@twins.programming.kicks-ass.net> In-Reply-To: <20160608064800.GN30154@twins.programming.kicks-ass.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMGEyZDcxYWItODkyOS00MGYwLTkwNzYtYzM5MDg1MjYxMDJmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Im9cL1JzYm1tZkFncUxmcG9FVzdvMEpETmNHOStaQjdVSkUrT2VPUUM3UmcwPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08.06.2016 Peter Zijlstra wrote: > How does this work in the light of intel_alt_er() ? Hi Peter, If the constrained bit is valid on only one of the OCR MSRs (like in case of KNL), then OCR valid mask will forbid altering it by the other MSR in intel_alt_er. If constrained bit is valid on both OCR MSR, so it can be safely altered by intel_alt_er, but in this case it should be defined twice - for each MSR i.e: INTEL_EEVENT_CONSTRAINT(0x01b7, 0, 0x1); // bit0 can be used only on PMC0 INTEL_EEVENT_CONSTRAINT(0x02b7, 0, 0x1); // bit0 can be used only on PMC0 I hope that answers your question. Thanks, Lukas