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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db8942cad4sm8565957a12.60.2025.01.23.02.02.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Jan 2025 02:02:49 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 23 Jan 2025 11:02:48 +0100 Message-Id: Cc: <~postmarketos/upstreaming@lists.sr.ht>, "AngeloGioacchino Del Regno" , "Konrad Dybcio" , "Martin Botka" , "Jami Kettunen" , , , , Subject: Re: [PATCH v2] drm/msm/dpu: Fall back to a single DSC encoder (1:1:1) on small SoCs From: "Luca Weiss" To: "Marijn Suijten" , "Rob Clark" , "Abhinav Kumar" , "Dmitry Baryshkov" , "Sean Paul" , "David Airlie" , "Simona Vetter" X-Mailer: aerc 0.19.0-0-gadd9e15e475d References: <20250122-dpu-111-topology-v2-1-505e95964af9@somainline.org> In-Reply-To: <20250122-dpu-111-topology-v2-1-505e95964af9@somainline.org> On Wed Jan 22, 2025 at 5:23 PM CET, Marijn Suijten wrote: > Some SoCs such as SC7280 (used in the Fairphone 5) have only a single > DSC "hard slice" encoder. The current hardcoded use of 2:2:1 topology > (2 LM and 2 DSC for a single interface) make it impossible to use > Display Stream Compression panels with mainline, which is exactly what's > installed on the Fairphone 5. > > By loosening the hardcoded `num_dsc =3D 2` to fall back to `num_dsc =3D > 1` when the catalog only contains one entry, we can trivially support > this phone and unblock further panel enablement on mainline. A few > more supporting changes in this patch ensure hardcoded constants of 2 > DSC encoders are replaced to count or read back the actual number of > DSC hardware blocks that are enabled for the given virtual encoder. > Likewise DSC_MODE_SPLIT_PANEL can no longer be unconditionally enabled. Still works fine, like v1! Tested-by: Luca Weiss Regards Luca > > Cc: Luca Weiss > Signed-off-by: Marijn Suijten > --- > Note that this doesn't paint the full picture in case there are SoCs > with more DSC hardware blocks, but when multiple virtual encoders > have already allocated most of them. My initial plan was to code > ahead for dynamically tracking and reallocating these blocks in RM, if > some virtual encoder could potentially be using too many DSC encoders > which, while "power optimal", may not be able to support the number of > requested displays/interfaces. Such a solution would automatically > ensure DSCmerge is *not* used when there are not enough hardware blocks > available in the first place. > --- > Changes in v2: > - Fairphone is one word, lowercase the P from phone (Luca); > - Skip unnecessary if (dpu_enc->dsc) check and always count the number > of non-NULL dpu_enc->hw_dsc[i] instead (Dmitry); > - Revert irrelevant whitespace cleanup in DSC comment, even if > worthless enough to send separately (Dmitry); > - Drop dsc_common_mode=3D0 initialization and move existing 0-assignment > from a random place in the function down to where this variable is > actually being updated (Dmitry); > - Link to v1: https://lore.kernel.org/r/20250121-dpu-111-topology-v1-1-d0= 1987205c53@somainline.org > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 47 +++++++++++++++--------= ------ > 1 file changed, 25 insertions(+), 22 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/dr= m/msm/disp/dpu1/dpu_encoder.c > index 5172ab4dea995a154cd88d05c3842d7425fc34ce..b585cd17462345f94bcc2ddd5= 7902cc7c312ae63 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -622,9 +622,9 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *dr= m_enc) > if (dpu_enc->phys_encs[i]) > intf_count++; > =20 > - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ > - if (dpu_enc->dsc) > - num_dsc =3D 2; > + for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) > + if (dpu_enc->hw_dsc[i]) > + num_dsc++; > =20 > return (num_dsc > 0) && (num_dsc > intf_count); > } > @@ -686,13 +686,19 @@ static struct msm_display_topology dpu_encoder_get_= topology( > =20 > if (dsc) { > /* > - * In case of Display Stream Compression (DSC), we would use > - * 2 DSC encoders, 2 layer mixers and 1 interface > - * this is power optimal and can drive up to (including) 4k > - * screens > + * Use 2 DSC encoders and 2 layer mixers per single interface > + * when Display Stream Compression (DSC) is enabled, > + * and when enough DSC blocks are available. > + * This is power-optimal and can drive up to (including) 4k > + * screens. > */ > - topology.num_dsc =3D 2; > - topology.num_lm =3D 2; > + if (dpu_kms->catalog->dsc_count >=3D 2) { > + topology.num_dsc =3D 2; > + topology.num_lm =3D 2; > + } else { > + topology.num_dsc =3D 1; > + topology.num_lm =3D 1; > + } > topology.num_intf =3D 1; > } > =20 > @@ -2020,7 +2026,6 @@ static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_= ctl *ctl, > static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, > struct drm_dsc_config *dsc) > { > - /* coding only for 2LM, 2enc, 1 dsc config */ > struct dpu_encoder_phys *enc_master =3D dpu_enc->cur_master; > struct dpu_hw_ctl *ctl =3D enc_master->hw_ctl; > struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; > @@ -2030,22 +2035,24 @@ static void dpu_encoder_prep_dsc(struct dpu_encod= er_virt *dpu_enc, > int dsc_common_mode; > int pic_width; > u32 initial_lines; > + int num_dsc =3D 0; > int i; > =20 > for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) { > hw_pp[i] =3D dpu_enc->hw_pp[i]; > hw_dsc[i] =3D dpu_enc->hw_dsc[i]; > =20 > - if (!hw_pp[i] || !hw_dsc[i]) { > - DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); > - return; > - } > + if (!hw_pp[i] || !hw_dsc[i]) > + break; > + > + num_dsc++; > } > =20 > - dsc_common_mode =3D 0; > pic_width =3D dsc->pic_width; > =20 > - dsc_common_mode =3D DSC_MODE_SPLIT_PANEL; > + dsc_common_mode =3D 0; > + if (num_dsc > 1) > + dsc_common_mode |=3D DSC_MODE_SPLIT_PANEL; > if (dpu_encoder_use_dsc_merge(enc_master->parent)) > dsc_common_mode |=3D DSC_MODE_MULTIPLEX; > if (enc_master->intf_mode =3D=3D INTF_MODE_VIDEO) > @@ -2054,14 +2061,10 @@ static void dpu_encoder_prep_dsc(struct dpu_encod= er_virt *dpu_enc, > this_frame_slices =3D pic_width / dsc->slice_width; > intf_ip_w =3D this_frame_slices * dsc->slice_width; > =20 > - /* > - * dsc merge case: when using 2 encoders for the same stream, > - * no. of slices need to be same on both the encoders. > - */ > - enc_ip_w =3D intf_ip_w / 2; > + enc_ip_w =3D intf_ip_w / num_dsc; > initial_lines =3D dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); > =20 > - for (i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) > + for (i =3D 0; i < num_dsc; i++) > dpu_encoder_dsc_pipe_cfg(ctl, hw_dsc[i], hw_pp[i], > dsc, dsc_common_mode, initial_lines); > } > > --- > base-commit: 1573c8d4cb206a2d1454ff711e79f8df2353290b > change-id: 20240204-dpu-111-topology-b12c1de82c8a > > Best regards,