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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5ebcd0dfe4esm1546076a12.73.2025.03.21.09.16.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Mar 2025 09:16:08 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 21 Mar 2025 17:16:07 +0100 Message-Id: Cc: "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Taniya Das" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 2/3] clk: qcom: Add video clock controller driver for SM6350 From: "Luca Weiss" To: "Dmitry Baryshkov" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250321-sm6350-videocc-v1-0-c5ce1f1483ee@fairphone.com> <20250321-sm6350-videocc-v1-2-c5ce1f1483ee@fairphone.com> In-Reply-To: On Fri Mar 21, 2025 at 4:55 PM CET, Dmitry Baryshkov wrote: > On Fri, Mar 21, 2025 at 03:45:00PM +0100, Luca Weiss wrote: >> From: Konrad Dybcio >>=20 >> Add support for the video clock controller found on SM6350 based >> devices. >>=20 >> Signed-off-by: Konrad Dybcio >> Co-developed-by: Luca Weiss >> Signed-off-by: Luca Weiss >> --- >> drivers/clk/qcom/Kconfig | 9 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/videocc-sm6350.c | 355 +++++++++++++++++++++++++++++++= +++++++ >> 3 files changed, 365 insertions(+) >>=20 >> + >> +/* 600 MHz */ >> +static const struct alpha_pll_config video_pll0_config =3D { >> + .l =3D 0x1F, > > Nit: lowercase hex please. No need to repost just for the sake of this > single line. Sounds like there'll be a v2 anyways with dts changes, so I'll fix it! Regards Luca > > Reviewed-by: Dmitry Baryshkov > > >> + .alpha =3D 0x4000, >> + .config_ctl_val =3D 0x20485699, >> + .config_ctl_hi_val =3D 0x00002067, >> + .test_ctl_val =3D 0x40000000, >> + .test_ctl_hi_val =3D 0x00000002, >> + .user_ctl_val =3D 0x00000101, >> + .user_ctl_hi_val =3D 0x00004005, >> +}; >> + >>=20