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[89.66.237.154]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8fbe407520sm3908666b.43.2026.02.13.03.14.53 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 13 Feb 2026 03:14:55 -0800 (PST) Content-Type: text/plain; charset=utf-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.700.81.1.4\)) Subject: Re: [PATCH RFC v4 1/4] media: dt-bindings: Add Amlogic V4L2 video decoder From: Piotr Oniszczuk In-Reply-To: <58d57a6c-7c69-4f5b-a4c2-f34ef0238511@kernel.org> Date: Fri, 13 Feb 2026 12:14:43 +0100 Cc: Zhentao Guo , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20260213-b4-s4-vdec-upstream-v4-0-c7112d00d662@amlogic.com> <20260213-b4-s4-vdec-upstream-v4-1-c7112d00d662@amlogic.com> <75e55ceb-e6dd-47b5-a829-66f6fbb3e13e@amlogic.com> <2f68ee18-e9d9-4da6-900c-93a7663b3c9d@kernel.org> <598c161c-d157-40e5-992c-912540589d7e@amlogic.com> <58d57a6c-7c69-4f5b-a4c2-f34ef0238511@kernel.org> To: Krzysztof Kozlowski X-Mailer: Apple Mail (2.3826.700.81.1.4) > Wiadomo=C5=9B=C4=87 napisana przez Krzysztof Kozlowski = w dniu 13 lut 2026, o godz. 09:55: >=20 > On 13/02/2026 09:31, Zhentao Guo wrote: >>>>>>=20 >>>>> Why? What for? >>>>>=20 >>>>> What is canvas provider? >>>> The canvas provider is: drivers/soc/amlogic/meson-canvas.c >>> What is this "canvas" device. >> You can think of canvas as the agent through which the decoder = hardware=20 >> accesses DDR. >=20 > AGAIN: >=20 > What is the canvas device. Describe or point me to bindings describing > it. Your current bindings say that canvas is "a collection of metadata > that describes a pixel buffer" so there is no way it handles DDR = access. >=20 > NAK >=20 >>>> In short, canvas is a hardware IP inside the Amlogic SoC. The = decoder IP >>>> needs to access DDR through canvas IP, so we need to reference the >>> Why decoder cannot access DDR directly? >> The internal topology of the S4 chip is designed this way, we don't = know=20 >> why our VLSI colleauges designed like this. But similar designs have=20= >> been removed in subsequent chips, eliminating the need to rely on a=20= >> common hardware IP. >=20 > Quite poor explanation. Based on this, this as well could be entry in > device reg lists. >=20 > Anyway, I am done guessing, explain properly the hardware instead of > answering with half-baked responses just so I will go away. >=20 >=20 > Best regards, > Krzysztof >=20 Krzysztof, May you pls explain me: what added value - to upstreaming aml video = decoder - will be provided by giving NAK .... because canvas/DDR access = details explanations are not enough detailed FOR YOU?