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[31.151.138.250]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6ed6b009sm609885766b.138.2025.04.28.04.26.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Apr 2025 04:26:06 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 28 Apr 2025 13:26:05 +0200 Message-Id: From: "Luca Weiss" To: "Ziqi Chen" , , , , , , , , , , , Cc: , , "Neil Armstrong" , "Matthias Brugger" , "AngeloGioacchino Del Regno" , "open list:ARM/Mediatek SoC support:Keyword:mediatek" , "moderated list:ARM/Mediatek SoC support:Keyword:mediatek" , "moderated list:ARM/Mediatek SoC support:Keyword:mediatek" Subject: Re: [PATCH v5 0/8] Support Multi-frequency scale for UFS X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250213080008.2984807-1-quic_ziqichen@quicinc.com> <29c3852c-3218-4b42-bc41-75721a95fccc@quicinc.com> In-Reply-To: <29c3852c-3218-4b42-bc41-75721a95fccc@quicinc.com> Hi Ziqi, On Mon Apr 28, 2025 at 10:06 AM CEST, Ziqi Chen wrote: > Hi Luca, > > We made changes to fix this special platform issue and verified it can > fix this issue. > Could you help double check if attached 3 patched can fix it from you sid= e? > If it is OK from you side as well, we will submit the final patches to > upstream With these 3 patches applied the errors are gone and I don't see any UFS-related warnings/errors in dmesg anymore. Let me know if I should check on anything else. Thanks for the quick fix! Regards Luca > > Thanks a lot~ > > BRs > Ziqi > > On 4/27/2025 4:14 PM, Ziqi Chen wrote: >> Hi Luca, >>=20 >> Thanks for your report. >> Really,=C2=A0 6350 is a special platform that the UFS_PHY_AXI_CLK doesn'= t >> match to the UFS_PHY_UNIPRO_CORE_CLK. We already found out the root >> cause and discussing the fix. We will submit change to fix this corner >> case. >>=20 >> BRs >> Ziqi >>=20 >> On 4/26/2025 3:48 AM, Luca Weiss wrote: >>> Hi Ziqi, >>> >>> On Thu Feb 13, 2025 at 9:00 AM CET, Ziqi Chen wrote: >>>> With OPP V2 enabled, devfreq can scale clocks amongst multiple frequen= cy >>>> plans. However, the gear speed is only toggled between min and max=20 >>>> during >>>> clock scaling. Enable multi-level gear scaling by mapping clock=20 >>>> frequencies >>>> to gear speeds, so that when devfreq scales clock frequencies we can p= ut >>>> the UFS link at the appropraite gear speeds accordingly. >>> >>> I believe this series is causing issues on SM6350: >>> >>> [=C2=A0=C2=A0=C2=A0 0.859449] ufshcd-qcom 1d84000.ufshc: ufs_qcom_freq_= to_gear_speed:=20 >>> Unsupported clock freq : 200000000 >>> [=C2=A0=C2=A0=C2=A0 0.886668] ufshcd-qcom 1d84000.ufshc: UNIPRO clk fre= q 200 MHz not=20 >>> supported >>> [=C2=A0=C2=A0=C2=A0 0.903791] devfreq 1d84000.ufshc: dvfs failed with (= -22) error >>> >>> That's with this patch, I actually haven't tried without on v6.15-rc3 >>> https://lore.kernel.org/all/20250314-sm6350-ufs-things-=20 >>> v1-2-3600362cc52c@fairphone.com/ >>> >>> I believe the issue appears because core clk and unipro clk rates don't >>> match on this platform, so this 200 MHz for GCC_UFS_PHY_AXI_CLK is not = a >>> valid unipro clock rate, but for GCC_UFS_PHY_UNIPRO_CORE_CLK it's >>> specified to 150 MHz in the opp table. >>> >>> Regards >>> Luca >>> >>>> >>>> This series has been tested on below platforms - >>>> sm8550 mtp + UFS3.1 >>>> SM8650 MTP + UFS3.1 >>>> SM8750 MTP + UFS4.0 >>=20