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From: "Diederik de Haas" To: "Piotr Zalewski" Cc: , , , , , , , , "Dang Huynh" , , , , Subject: Re: [PATCH drm-misc-next] rockchip/drm: vop2: don't check color_mgmt_changed in atomic_enable References: <20241206192013.342692-3-pZ010001011111@proton.me> <4z0y_F1ZT_xfO0-DwU-D5NwL3t3wHuGmivOB3QFjDsn0hzpz_hOeU63pRVBIgSU1j89jmYPq-TJHPqMCj3fAygwwX6IaPoVsqKqVi2jxmCc=@proton.me> In-Reply-To: <4z0y_F1ZT_xfO0-DwU-D5NwL3t3wHuGmivOB3QFjDsn0hzpz_hOeU63pRVBIgSU1j89jmYPq-TJHPqMCj3fAygwwX6IaPoVsqKqVi2jxmCc=@proton.me> X-Migadu-Flow: FLOW_OUT --1a690bef81fb6f944ba894a0b6204d1559cb35f27fa37f9df3ad43d1b8ff Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi Piotr, On Tue Jun 10, 2025 at 12:37 AM CEST, Piotr Zalewski wrote: > Hi Diederik, sorry for late response No need to be sorry :-) (late? Less then 2 days vs my ~4 months before the git bisect ...) >> Interesting that it also happened with drm=3Dy. > > I actually checked now and i don't have the issue with drm=3Dy, sorry for= =20 > misinforming you all, hopefully no one's time was wasted. Good to know, thanks :-) >> > happened twice and at short interval and since this patch allows for g= amma >> > LUT update regardless of color_mgmt_changed state this makes DSP CTRL = GAMMA >> > LUT EN bit to be unset twice too. It seems that VOP does not like it. = I >>=20 >> Happy to see you found the cause :-) >> Do you happen to know why it was unset twice? That sounds suboptimal. > > It is due to DRM modeset which can happens when CRTC (display) config cha= nges=20 > "significantly". AFAIK modeset happens def. when you go out of suspend or > display timings change. I might have been fooled by serial console last t= ime > as it does not appear to happen twice in short interval when i review the= =20 > journal entries. > >> But (IIUC) setting a bit to a value it already has causing issues, >> sounds surprising as well. > > Depends on what hardware does, when you write to a register it might caus= e > many other things to happen and seems like for vop2 it messes something u= p. I didn't know that, thanks. > I made a second patch so that the first write is not permitted but all=20 > subsequent are permitted (regardless of lut en state) - issue disappeared= =20 > too. So it might be that very first write to dsp lut disable happens too= =20 > fast (in relation to something else)?. It is not intuitive because when d= rm is > a module it happens usually like ~second later. > > part of the log with drm=3Dy > ``` > [ 6.543099] rockchip-drm display-subsystem: [drm] GAMMA LUT DISABLE > ``` > > part of the log with drm=3Dm > ``` > [ 7.944120] rockchip-drm display-subsystem: [drm] GAMMA LUT DISABLE > ``` My first (uneducated) hunch was a timing issue and ``=3Dm`` can reveal issues which you wouldn't see with ``=3Dy``. Andy already found an issue "that shouldn't happen" and my latest test also had an unexpected result. So (eventually) we'll figure it out :-) >> Sounds like a plan. It could be that this issue surfaced an underlaying >> issue and if so, fixing that would be even better. > > When i have time this week I will check on what version of the kernel i= =20 > tested gamma lut when i sent the patches and test there. I think it would be beneficial if you'd do the tests that Andy asked 'me' to do too, so we can compare results. FWIW: I have the 4GB RAM version. Cheers, Diederik --1a690bef81fb6f944ba894a0b6204d1559cb35f27fa37f9df3ad43d1b8ff Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQT1sUPBYsyGmi4usy/XblvOeH7bbgUCaEgWmQAKCRDXblvOeH7b bga5AP46kC7i4GeX+4vWp7Yxj8oZG/p/M87NvkPeVbBlmVSxNwD/aKazZBYfZhA9 N8AQj5r2cn8N8/pLuRozO0FJiPY+iAk= =thoO -----END PGP SIGNATURE----- --1a690bef81fb6f944ba894a0b6204d1559cb35f27fa37f9df3ad43d1b8ff--