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Mon, 23 Jun 2025 03:04:31 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 23 Jun 2025 12:04:30 +0200 Message-Id: Subject: Re: [External] Re: [PATCH] RISC-V: KVM: Delegate illegal instruction fault Cc: , , , , , , , , , , "linux-riscv" To: "Xu Lu" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20250620091720.85633-1-luxu.kernel@bytedance.com> In-Reply-To: 2025-06-22T18:11:49+08:00, Xu Lu : > Hi Radim, > > On Fri, Jun 20, 2025 at 8:04=E2=80=AFPM Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: >> >> 2025-06-20T17:17:20+08:00, Xu Lu : >> > Delegate illegal instruction fault to VS mode in default to avoid such >> > exceptions being trapped to HS and redirected back to VS. >> > >> > Signed-off-by: Xu Lu >> > --- >> > diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/as= m/kvm_host.h >> > @@ -48,6 +48,7 @@ >> > + BIT(EXC_INST_ILLEGAL) | \ >> >> You should also remove the dead code in kvm_riscv_vcpu_exit. > > I only want to delegate it by default. And KVM may still want to > delegate different exceptions for different VMs like what it does for > EXC_BREAKPOINT. (I think we could easily reintroduce the code if KVM wants to do that in the future. I also think that it's bad that this patch is doing an observable change without userspace involvement -- the counting of KVM SBI PMU events, but others will probably disagree with me on this.) > So maybe it is better to reserve these codes? Possibly, the current is acceptable if you have considered the implications on PMU events. >> And why not delegate the others as well? >> (EXC_LOAD_MISALIGNED, EXC_STORE_MISALIGNED, EXC_LOAD_ACCESS, >> EXC_STORE_ACCESS, and EXC_INST_ACCESS.) > > Thanks for the reminder. I will have a test and resend the patch if it wo= rks. The misaligned exceptions are already being worked on, so don't waste your time on them, sorry.