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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f6b6007fsm860633366b.166.2025.07.08.03.28.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Jul 2025 03:28:01 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 08 Jul 2025 12:28:00 +0200 Message-Id: Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 2/2] interconnect: qcom: Add SM7635 interconnect provider driver From: "Luca Weiss" To: "Konrad Dybcio" , "Georgi Djakov" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250625-sm7635-icc-v1-0-8b49200416b0@fairphone.com> <20250625-sm7635-icc-v1-2-8b49200416b0@fairphone.com> <3f8bcecb-4c5e-48b1-98be-96f3c0c8329e@oss.qualcomm.com> In-Reply-To: <3f8bcecb-4c5e-48b1-98be-96f3c0c8329e@oss.qualcomm.com> Hi Konrad, On Fri Jun 27, 2025 at 2:48 PM CEST, Konrad Dybcio wrote: > On 6/25/25 11:13 AM, Luca Weiss wrote: >> Add driver for the Qualcomm interconnect buses found in SM7635 based >> platforms. The topology consists of several NoCs that are controlled by >> a remote processor that collects the aggregated bandwidth for each >> master-slave pairs. >>=20 >> Signed-off-by: Luca Weiss >> --- > > [...] > >> +static const struct of_device_id qnoc_of_match[] =3D { >> + { .compatible =3D "qcom,sm7635-aggre1-noc", >> + .data =3D &sm7635_aggre1_noc}, >> + { .compatible =3D "qcom,sm7635-aggre2-noc", >> + .data =3D &sm7635_aggre2_noc}, >> + { .compatible =3D "qcom,sm7635-clk-virt", >> + .data =3D &sm7635_clk_virt}, >> + { .compatible =3D "qcom,sm7635-cnoc-cfg", >> + .data =3D &sm7635_cnoc_cfg}, >> + { .compatible =3D "qcom,sm7635-cnoc-main", >> + .data =3D &sm7635_cnoc_main}, >> + { .compatible =3D "qcom,sm7635-gem-noc", >> + .data =3D &sm7635_gem_noc}, >> + { .compatible =3D "qcom,sm7635-lpass-ag-noc", >> + .data =3D &sm7635_lpass_ag_noc}, >> + { .compatible =3D "qcom,sm7635-mc-virt", >> + .data =3D &sm7635_mc_virt}, >> + { .compatible =3D "qcom,sm7635-mmss-noc", >> + .data =3D &sm7635_mmss_noc}, >> + { .compatible =3D "qcom,sm7635-nsp-noc", >> + .data =3D &sm7635_nsp_noc}, >> + { .compatible =3D "qcom,sm7635-pcie-anoc", >> + .data =3D &sm7635_pcie_anoc}, >> + { .compatible =3D "qcom,sm7635-system-noc", >> + .data =3D &sm7635_system_noc}, > > One line per entry, please > > In addition to what Dmitry asked for, please also look into porting > QoS settings - those will require additional clock references in the ICC > nodes and as such, the bindings will be altered (which we'd prefer to get > right from the getgo). I've forgotten to do this for v2, which I've just sent. But we already have the clock references in the bindings, so the bindings should be final, also when QoS is added, so just a driver patch then. I will put this on my todo list for a future patch to enable this, if that's fine with you. > As far as testing goes, there may not be any apparent perf changes, but > if you get the clocks list wrong, the device will lock up at boot (unless > you're booting with clk_ignore_unused and friends) Ack Regards Luca > > Konrad