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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e910e8sm140856366b.36.2025.07.10.07.09.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Jul 2025 07:09:33 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 10 Jul 2025 16:09:33 +0200 Message-Id: From: "Luca Weiss" To: "Konrad Dybcio" , "Greg Kroah-Hartman" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Wesley Cheng" , "Vinod Koul" , "Kishon Vijay Abraham I" , "Abel Vesa" Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , , , "Neil Armstrong" Subject: Re: [PATCH v2 4/4] phy: qcom: phy-qcom-snps-eusb2: Add extra register write for Milos X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250709-sm7635-eusb-phy-v2-0-4790eeee7ae0@fairphone.com> <20250709-sm7635-eusb-phy-v2-4-4790eeee7ae0@fairphone.com> <7d073433-f254-4d75-a68b-d184f900294a@oss.qualcomm.com> In-Reply-To: On Thu Jul 10, 2025 at 2:29 PM CEST, Konrad Dybcio wrote: > On 7/10/25 2:25 PM, Luca Weiss wrote: >> On Thu Jul 10, 2025 at 2:10 PM CEST, Konrad Dybcio wrote: >>> On 7/9/25 11:18 AM, Luca Weiss wrote: >>>> As per the downstream devicetree for Milos, add a register write for >>>> QCOM_USB_PHY_CFG_CTRL_1 as per the "eUSB2 HPG version 1.0.2 update". >>>> >>>> Reviewed-by: Neil Armstrong >>>> Signed-off-by: Luca Weiss >>>> --- >>>> The downstream driver supports an arbitrary extra init sequence via >>>> qcom,param-override-seq. >>>> >>>> volcano-usb.dtsi has the following which is implemented in this patch: >>>> >>>> /* eUSB2 HPG version 1.0.2 update */ >>>> qcom,param-override-seq =3D >>>> <0x00 0x58>; >>>> --- >>>> drivers/phy/phy-snps-eusb2.c | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>>> >>>> diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2= .c >>>> index e232b8b4d29100b8fee9e913e2124788af09f2aa..87fc086424ba4d9fb3ce87= 0aa7f7971a51d4a567 100644 >>>> --- a/drivers/phy/phy-snps-eusb2.c >>>> +++ b/drivers/phy/phy-snps-eusb2.c >>>> @@ -420,6 +420,12 @@ static int qcom_snps_eusb2_hsphy_init(struct phy = *p) >>>> /* set default parameters */ >>>> qcom_eusb2_default_parameters(phy); >>>> =20 >>>> + if (of_device_is_compatible(p->dev.of_node, "qcom,milos-snps-eusb2-p= hy")) { >>>> + /* eUSB2 HPG version 1.0.2 update */ >>>> + writel_relaxed(0x0, phy->base + QCOM_USB_PHY_CFG_CTRL_1); >>>> + readl_relaxed(phy->base + QCOM_USB_PHY_CFG_CTRL_1); >>> >>> Said HPG asks to clear bits [7:1] on all targets >>=20 >> Okay, so make this unconditional and only update those bits instead of >> writing the full register? > > Yes > >>=20 >> Keep the write at this location, or move the code somewhere else in the >> function? > Let's simply do this instead: > > diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c > index 87f323e758d6..6c44d0366f34 100644 > --- a/drivers/phy/phy-snps-eusb2.c > +++ b/drivers/phy/phy-snps-eusb2.c > @@ -392,7 +392,7 @@ static int qcom_snps_eusb2_hsphy_init(struct phy *p) > =20 > snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_1, > PHY_CFG_PLL_CPBIAS_CNTRL_MASK, > - FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_M= ASK, 0x1)); > + FIELD_PREP(PHY_CFG_PLL_CPBIAS_CNTRL_M= ASK, 0x0)); > =20 > snps_eusb2_hsphy_write_mask(phy->base, QCOM_USB_PHY_CFG_CTRL_4, > PHY_CFG_PLL_INT_CNTRL_MASK Sounds reasonable, if the HPG suggests that... Just asking myself why this wasn't updated in the driver but only added via the qcom,param-override-seq for some SoCs. But downstream is still downstream I guess. Regards Luca > > > Konrad