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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: de.bosch.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DB9PR10MB4730.EURPRD10.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: b930bcdc-c806-4253-67b7-08dcee7fdb1e X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2024 07:46:48.4051 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0ae51e19-07c8-4e4b-bb6d-648ee58410f4 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: is5x7dUwi4KSG8/KYEVnyEYlEkp8le3c4CKv8Qvga/HsHeeDst21Fhndp1Vz6zWBRYKUBxICTc7p9KbsPIVw0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR10MB9005 >> >It should still need to place the two bytes of that 16 bit value in the= correct order to send to hardware. That may be handled via a 32 bit word = length on SPI though. >> >> >> This is the most confusing part. During the request preparation, we foc= us on the bit order not the byte order. We need to bring the 16 bit value i= n the correct bit order, to the correct bit position in the 32 bit request.= This is automatically guarantied using FIELD_PREP. FIELD_PREP shifts the d= ata 15-0 to request 18-3. We shall never manually change the byte order of = the 16 bit value. The byte order (of the whole request) becomes important w= hen we send it over spi, which will be explained later. >> >> >> >> In the SMI240, the register address is 8 bit and each register is 16 = bit. We do not have any register value, which is bigger than 16 bit and nee= d to be stored in multiple registers. Therefore the device does not need e= ndian. Neither big endian nor Little Endian. To access the register, it is= important to prepare the request frame according to the specification. >> >> >> >> A request is 32 bit >> >> >> >> ID ADR W CAP * WDATA CRC >> >> 31-30 29-22 21 20 19 18-3 2-0 >> >> >> >> ID: device id (if more than 1 device) >> >> ADR: reg address >> >> W: write/read >> >> CAP: capture mode on/off >> >> *: reserved >> >> WDATA : reg value bit 15-0 >> >> CRC: check sum >> >> >> >> To prepare the request properly, the bit order is here critical. We n= eed to put each part in its bit position. The request is created as a local= u32, with help of FIELD_PREP, we put the value of each part to its bit pos= ition. FIELD_PREP will take care of the cpu endian and always put the value= to the correct bit position. Before we send the request via SPI, a cpu end= ian to big endian conversion is required. >> > >> >So there are two possibilities here. Either the byte order is just rev= ersed for the device in which case fine as you describe or perhaps the SPI = transfers should be using a 32 bit word? You'd do that by overriding the b= its_per_word in the individual SPI transfers. >> > >> > >> >> Since the spi bus transfers data using big endian. When we get the re= sponse from spi, the response is big endian and need to be converted in cpu= endian. Any other manually endian conversion is not required. >> > >> >The SPI bus itself has no real concept of endian as such. It just sends= bits in the order it is fed them. The device may require a particular ord= ering of course if we assume it makes sense to break the transfers up into = byte size chnunks. >> >> >> Yes, the device expect that the 32 bit request will be sent from MSBit t= o LSBit. Which means the ID shall be sent firstly, followed by ADR, W, CAP,= *, WDATA, CRC. If we consider the 32 bit as 4 bytes , then the MSB need t= o sent firstly, and followed by the LSBs. From this perspective we can say = that the SMI240 SPI protocol requires big endian. On the host side the requ= est is a local u32 (4 bytes). To make sure that the MSB will be sent firstl= y we need to convert the request to big endian before sending it over spi. > >Understood. Try a 32 bit word size for the spi transfers. I think that sh= ould make everything work without any need to make it big endian. > We tried to use 32 bit word size for the spi transfers. Nevertheless not al= l the spi libraries supports 32 bit word. A number of spi library just supp= ort 8bit. Therefore we will firstly provide a 8bit spi transfer in next ver= sion.=20 Best Regards Jianping Shen