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Brown" Subject: Re: [PATCH RESEND v4 4/4] drm/bridge: nwl-dsi: Correct MIPI DSI horizontal sync timing Date: Sun, 25 Oct 2026 07:55:10 +0100 Message-ID: In-Reply-To: <20261014-nwl-dsi-fixes-v4-4-b9138ea5e12c@geanix.com> References: <20261014-nwl-dsi-fixes-v4-0-b9138ea5e12c@geanix.com> <20261014-nwl-dsi-fixes-v4-4-b9138ea5e12c@geanix.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On =C5=9Broda, 14 pa=C5=BAdziernika 2026 09:44:45 czas =C5=9Brodkowoeuropej= ski standardowy=20 Esben Haabendal wrote: > The NWL MIPI Host controller registers specifies the horizontal front > porch, sync pulse, and back porch in DSI packet payload size in bytes (ie. > not in pixel clocks). >=20 > The calculation for this is (mostly) described in section 13.6.3.5.1.2 of > the i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors Reference > Manual (rev. 3.1). The formula shown there does not take packet header si= ze > into account though. >=20 > The formula implemented here converts the hfp, hsa, and hbp to DSI packet > bytes and then subtracts the number of packet header bytes. >=20 > It is worth noting that these values only needs to match approximately, > according to the reference manual. >=20 > Based on commit in NXP vendor tree > commit f2a61699749d ("LF-7981-4: drm/bridge: nwl-dsi: Correct MIPI DSI > horizontal sync timing") >=20 > Signed-off-by: Esben Haabendal > Cc: Robert Chiras > Cc: Oliver F. Brown This lets the Librem 5 screen be driven without additional timing hacks. Tested-by: Sebastian Krzyszkowiak