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From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Zhi Wang" <zhiw@nvidia.com>, <rust-for-linux@vger.kernel.org>
Cc: <dakr@kernel.org>, <bhelgaas@google.com>,
	<kwilczynski@kernel.org>, <ojeda@kernel.org>,
	<alex.gaynor@gmail.com>, <boqun.feng@gmail.com>,
	<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
	<lossin@kernel.org>, <a.hindborg@kernel.org>,
	<aliceryhl@google.com>, <tmgross@umich.edu>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<cjia@nvidia.com>, <smitra@nvidia.com>, <ankita@nvidia.com>,
	<aniketa@nvidia.com>, <kwankhede@nvidia.com>,
	<targupta@nvidia.com>, <zhiwang@kernel.org>,
	<acourbot@nvidia.com>, <joelagnelf@nvidia.com>,
	<jhubbard@nvidia.com>, <markus.probst@posteo.de>
Subject: Re: [PATCH v2 0/5] rust: pci: add config space read/write support, take 1
Date: Tue, 21 Oct 2025 23:07:27 +0900	[thread overview]
Message-ID: <DDO24JQ1I3ER.1GOOI7RQISUS@nvidia.com> (raw)
In-Reply-To: <20251016210250.15932-1-zhiw@nvidia.com>

On Fri Oct 17, 2025 at 6:02 AM JST, Zhi Wang wrote:
> In the NVIDIA vGPU RFC [1], the PCI configuration space access is
> required in nova-core for preparing gspVFInfo when vGPU support is
> enabled. This series is the following up of the discussion with Danilo
> for how to introduce support of PCI configuration space access in Rust
> PCI abstrations. Bascially, we are thinking of introducing another
> backend for PCI configuration space access similar with Kernel::Io.
>
> This ideas of this series are:
>
> - Factor out a common trait 'Io' for other accessors to share the
>   same compiling/runtime check like before.
>
> - Factor the MMIO read/write macros from the define_read! and
>   define_write! macros. Thus, define_{read, write}! can be used in other
>   backend.
>
> - Add a helper to query configuration space size. This is mostly for
>   runtime check.
>
> - Implement the PCI configuration space access backend in PCI
>   abstractions.
>
> v2:
>
> - Factor out common trait as 'Io' and keep the rest routines in original
>   'Io' as 'Mmio'. (Danilo)
>
> - Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implemention to use
>   'MmioRaw'.
>
> - Intorduce pci::Device<Bound>::config_space(). (Danilo)
>
> - Implement both infallible and fallible read/write routines, the device
>   driver devicdes which version should be used.
>
> Moving forward:
>
> - Define and use register! macros.
> - Introduce { cap, ecap } search and read.
>
> RFC v1:
> https://lore.kernel.org/all/20251010080330.183559-1-zhiw@nvidia.com/

One small nit: the title of this series 

    [PATCH v2 0/5] rust: pci: add config space read/write support, take 1

Is a tad confusing. How can this be take 1, if this is a v2? Also there
is no v1, the previous revision was a RFC.

Technically this should have been [PATCH 0/5] or [PATCH v1 0/5]. `b4` is
great to avoid this kind of problems, and a huge time saver generally
speaking. Can't recommend it enough.

      parent reply	other threads:[~2025-10-21 14:07 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-16 21:02 Zhi Wang
2025-10-16 21:02 ` [PATCH v2 1/5] rust/io: factor common I/O helpers into Io trait and specialize Mmio<SIZE> Zhi Wang
2025-10-17  1:26   ` Bjorn Helgaas
2025-10-17 10:56   ` Danilo Krummrich
2025-10-20 11:44   ` Alexandre Courbot
2025-10-20 19:34   ` John Hubbard
2025-10-20 23:36   ` kernel test robot
2025-10-16 21:02 ` [PATCH v2 2/5] rust: io: factor out MMIO read/write macros Zhi Wang
2025-10-17 11:01   ` Danilo Krummrich
2025-10-16 21:02 ` [PATCH v2 3/5] rust: pci: add a helper to query configuration space size Zhi Wang
2025-10-17 11:09   ` Danilo Krummrich
2025-10-16 21:02 ` [PATCH v2 4/5] rust: pci: add config space read/write support Zhi Wang
2025-10-16 21:02 ` [PATCH v2 5/5] nova-core: test configuration routine Zhi Wang
2025-10-17  4:55   ` Zhi Wang
2025-10-17 11:11     ` Danilo Krummrich
2025-10-21 14:07 ` Alexandre Courbot [this message]

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