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charset=UTF-8 Date: Wed, 29 Oct 2025 23:05:47 +0900 Message-Id: Cc: "Alexandre Courbot" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , "Edwin Peer" , "Zhi Wang" , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , , "LKML" , "Nouveau" Subject: Re: [PATCH v3 2/2] gpu: nova-core: add boot42 support for next-gen GPUs From: "Alexandre Courbot" To: "John Hubbard" , "Danilo Krummrich" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20251029030332.514358-1-jhubbard@nvidia.com> <20251029030332.514358-3-jhubbard@nvidia.com> In-Reply-To: <20251029030332.514358-3-jhubbard@nvidia.com> X-ClientProxiedBy: TYCP286CA0244.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:456::19) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LV3PR12MB9168:EE_ X-MS-Office365-Filtering-Correlation-Id: 051b080f-1d12-41d6-4fdd-08de16f4445a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|10070799003|1800799024|376014|7416014; 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> =20 > impl NV_PMC_BOOT_0 { > + pub(crate) fn is_nv04(self) -> bool { > + // The very first supported GPU was NV04, and it is identified b= y a specific bit pattern in > + // boot0. This provides a way to check for that, which in turn i= s required in order to avoid > + // confusing future "next-gen" GPUs with NV04. > + self.architecture_0() =3D=3D 0 && (self.0 & 0xff00fff0) =3D=3D 0= x20004000 > + } > + > + pub(crate) fn is_next_gen(self) -> bool { > + // "next-gen" GPUs (some time after Blackwell) will set `archite= cture_0` to 0, and put the > + // architecture details in boot42 instead. > + self.architecture_0() =3D=3D 0 && !self.is_nv04() > + } > /// Combines `architecture_0` and `architecture_1` to obtain the arc= hitecture of the chip. > pub(crate) fn architecture(self) -> Result { > Architecture::try_from( > @@ -43,6 +55,21 @@ pub(crate) fn chipset(self) -> Result { > } > } > =20 > +register!(NV_PMC_BOOT_42 @ 0x00000108, "Extended architecture informatio= n" { > + 7:0 implementation as u8, "Implementation version of the archite= cture"; > + 15:8 architecture as u8, "Architecture value"; Here you can directly return the `Architecture` type and spare callers the labor of doing the conversion themselves: 15:8 architecture as u8 ?=3D> Architecture, "Architecture value"; This allows the implementation of `NV_PMC_BOOT_42` to mirror that of `NV_PMC_BOOT_0`: impl NV_PMC_BOOT_42 { pub(crate) fn chipset(self) -> Result { self.architecture() .map(|arch| { ((arch as u32) << Self::IMPLEMENTATION_RANGE.len()) | u32::from(self.implementation()) }) .and_then(Chipset::try_from) } } ... but also requires `Architecture` to be `repr(u8)` and to implement `Default` and `Into` so it can be used in the `register` macro: /// Enum representation of the GPU generation. #[derive(fmt::Debug, Default)] #[repr(u8)] pub(crate) enum Architecture { #[default] Turing =3D 0x16, Ampere =3D 0x17, Ada =3D 0x19, } impl From for u8 { fn from(value: Architecture) -> Self { // CAST: `Architecture` is `repr(u8)`, so this cast is always los= sless. value as u8 } } These implementations were not needed for `NV_PMC_BOOT_0` because its `architecture` method is manually implemented as it depends on two distinct fields.