From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Zhi Wang" <zhiw@nvidia.com>, <rust-for-linux@vger.kernel.org>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <dakr@kernel.org>, <aliceryhl@google.com>, <bhelgaas@google.com>,
<kwilczynski@kernel.org>, <ojeda@kernel.org>,
<alex.gaynor@gmail.com>, <boqun.feng@gmail.com>,
<gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
<lossin@kernel.org>, <a.hindborg@kernel.org>, <tmgross@umich.edu>,
<markus.probst@posteo.de>, <helgaas@kernel.org>,
<cjia@nvidia.com>, <smitra@nvidia.com>, <ankita@nvidia.com>,
<aniketa@nvidia.com>, <kwankhede@nvidia.com>,
<targupta@nvidia.com>, <acourbot@nvidia.com>,
<joelagnelf@nvidia.com>, <jhubbard@nvidia.com>,
<zhiwang@kernel.org>
Subject: Re: [PATCH v6 RESEND 6/7] rust: pci: add config space read/write support
Date: Thu, 13 Nov 2025 16:56:28 +0900 [thread overview]
Message-ID: <DE7EN1I1WCL8.39OE95LPS6XXH@nvidia.com> (raw)
In-Reply-To: <20251110204119.18351-7-zhiw@nvidia.com>
On Tue Nov 11, 2025 at 5:41 AM JST, Zhi Wang wrote:
> Drivers might need to access PCI config space for querying capability
> structures and access the registers inside the structures.
>
> For Rust drivers need to access PCI config space, the Rust PCI abstraction
> needs to support it in a way that upholds Rust's safety principles.
>
> Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe
> accessors for PCI config space. The new type implements the `Io` trait to
> share offset validation and bound-checking logic with others.
>
> Cc: Danilo Krummrich <dakr@kernel.org>
> Signed-off-by: Zhi Wang <zhiw@nvidia.com>
> ---
> rust/kernel/pci.rs | 41 ++++++++++++++++++++++-
> rust/kernel/pci/io.rs | 75 ++++++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 114 insertions(+), 2 deletions(-)
>
> diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
> index 410b79d46632..d8048c7d0f32 100644
> --- a/rust/kernel/pci.rs
> +++ b/rust/kernel/pci.rs
> @@ -39,7 +39,10 @@
> ClassMask,
> Vendor, //
> };
> -pub use self::io::Bar;
> +pub use self::io::{
> + Bar,
> + ConfigSpace, //
> +};
> pub use self::irq::{
> IrqType,
> IrqTypes,
> @@ -330,6 +333,28 @@ fn as_raw(&self) -> *mut bindings::pci_dev {
> }
> }
>
> +/// Represents the size of a PCI configuration space.
> +///
> +/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
> +/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
> +/// specification.
The comment says this is either, but below we have:
> @@ -141,4 +200,18 @@ pub fn iomap_region<'a>(
> ) -> impl PinInit<Devres<Bar>, Error> + 'a {
> self.iomap_region_sized::<0>(bar, name)
> }
> +
> + /// Return an initialized config space object.
> + pub fn config_space<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Normal.as_raw() }>> {
> + Ok(ConfigSpace { pdev: self })
> + }
> +
> + /// Return an initialized config space object.
> + pub fn config_space_exteneded<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Extended.as_raw() }>> {
> + Ok(ConfigSpace { pdev: self })
> + }
> }
(typo on "exteneded" btw)
Which means that a caller can infallibly (both methods return a `Result`
but can never fail, for some reason) create a `ConfigSpace` that does
not match its actual size.
That's particularly a problem is `cfg_size` returns `256` but we call
`config_space_extended`, as the returned `ConfigSpace` will have a
`maxsize` that is smaller than its `MIN_SIZE`...
I guess we should either validate the size using `cfg_size` before
creating and returning the `ConfigSpace`, or have a single method that
returns a Result containing an enum which variants are the supported
sizes?
I am also wondering whether we want `ConfigSpace` to be generic over a
constant - it makes it possible to have instances or arbitrary size, and
makes them a bit cumbersome to define as we need to do something like
`ConfigSpace<'a, { ConfigSpaceSize::Extended.as_raw() }>`.
Maybe we can use types instead, e.g.
pub trait ConfigSpaceSize {
const MIN_SIZE: usize;
}
pub enum Normal {}
impl ConfigSpaceSize for Normal {
const MIN_SIZE: usize = 256;
}
pub enum Extended {}
impl ConfigSpaceSize for Extended {
const MIN_SIZE: usize = 4096;
}
pub struct ConfigSpace<'a, S: ConfigSpaceSize> {
...
impl<'a, const SIZE: usize> Io for ConfigSpace<'a, S: ConfigSpaceSize> {
const MIN_SIZE: usize = S::MIN_SIZE;
...
And then `cfg_size` could be replaced by just `config_space` which
returns an enum of the possible `ConfigSpace`s supported, that the
caller needs to match against.
Just an idea for your consideration, I don't know whether that would
actually work better. :)
next prev parent reply other threads:[~2025-11-13 7:56 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 20:41 [PATCH v6 RESEND 0/7] " Zhi Wang
2025-11-10 20:41 ` [PATCH v6 RESEND 1/7] samples: rust: rust_driver_pci: use "kernel vertical" style for imports Zhi Wang
2025-11-10 20:41 ` [PATCH v6 RESEND 2/7] rust: devres: " Zhi Wang
2025-11-10 20:41 ` [PATCH v6 RESEND 3/7] rust: io: " Zhi Wang
2025-11-10 20:41 ` [PATCH v6 RESEND 4/7] rust: io: factor common I/O helpers into Io trait Zhi Wang
2025-11-13 7:36 ` Alexandre Courbot
2025-11-14 12:58 ` Alice Ryhl
2025-11-14 17:27 ` Zhi Wang
2025-11-14 18:53 ` Tamir Duberstein
2025-11-17 17:14 ` Zhi Wang
2025-11-14 20:31 ` Danilo Krummrich
2025-11-17 22:44 ` John Hubbard
2025-11-18 21:18 ` Danilo Krummrich
2025-11-18 23:43 ` John Hubbard
2025-11-10 20:41 ` [PATCH v6 RESEND 5/7] rust: io: factor out MMIO read/write macros Zhi Wang
2025-11-13 7:36 ` Alexandre Courbot
2025-11-14 16:06 ` Zhi Wang
2025-11-10 20:41 ` [PATCH v6 RESEND 6/7] rust: pci: add config space read/write support Zhi Wang
2025-11-13 7:56 ` Alexandre Courbot [this message]
2025-11-14 16:59 ` Zhi Wang
2025-11-14 0:20 ` Joel Fernandes
2025-11-17 20:28 ` Zhi Wang
2025-11-17 22:07 ` Danilo Krummrich
2025-11-10 20:41 ` [PATCH v6 RESNED 7/7] sample: rust: pci: add tests for config space routines Zhi Wang
2025-11-11 0:01 ` [PATCH v6 RESEND 0/7] rust: pci: add config space read/write support Joel Fernandes
2025-11-11 8:43 ` Zhi Wang
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