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Wed, 03 Dec 2025 20:07:23 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 04 Dec 2025 13:07:20 +0900 Message-Id: Subject: Re: [PATCH v3 5/8] riscv: smp: use NMI for CPU stop Cc: "linux-riscv" To: "Yunhui Cui" , , , , , , , , , , , , , , , , , , , , , , , , , From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20251127125305.89961-1-cuiyunhui@bytedance.com> <20251127125305.89961-6-cuiyunhui@bytedance.com> In-Reply-To: <20251127125305.89961-6-cuiyunhui@bytedance.com> 2025-11-27T20:53:02+08:00, Yunhui Cui : > Use NMI instead of IPI for CPU stop if RISC-V SSE NMI is supported. > > Signed-off-by: Yunhui Cui > --- > diff --git a/drivers/firmware/riscv/riscv_sse_nmi.c b/drivers/firmware/ri= scv/riscv_sse_nmi.c > @@ -58,6 +58,7 @@ static int local_nmi_handler(u32 evt, void *arg, struct= pt_regs *regs) > type =3D atomic_read(this_cpu_ptr(&local_nmi)); > =20 > NMI_HANDLE(LOCAL_NMI_CRASH, cpu_crash_stop, cpu, regs); > + NMI_HANDLE(LOCAL_NMI_STOP, cpu_stop); Please document the intended preemption design for all SSE events, because it will be a nightmare if we forget some assumptions in the coming years. (That includes the relative priorities of RAS/PMU/...) Thanks.