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Fri, 09 Jan 2026 21:29:31 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 09 Jan 2026 23:29:29 -0600 Message-Id: Subject: Re: [PATCH 2/2] arm64: mte: Defer disabling of TCO until user_access_begin/end From: "Taehyun Noh" To: "Catalin Marinas" , "Will Deacon" Cc: "Carl Worth" , , , , , X-Mailer: aerc 0.20.1 References: <20251030-mte-tighten-tco-v1-2-88c92e7529d9@os.amperecomputing.com> In-Reply-To: Hi, On Thu Jan 8, 2026 at 12:45 PM CST, Catalin Marinas wrote: > Reading the Arm ARM section again, I wonder whether always setting TCMA1 > does the trick for the Ampere hardware. With KASAN disabled in the > kernel, all addresses will star with 0xff... so behave as match-all. We > do this with KASAN_HW_TAGS enabled but it won't have any effect with > kasan disabled. Our team agrees with Catalin=E2=80=99s TCMA1 solution. It disables every ke= rnel tag checking but the user address will get tag checked as far as TCO is clear. Also, Carl=E2=80=99s initial testing confirms that `mem_access_checked*:k` counters drop with the TCMA1 patch. While we haven=E2=80=99t run the memcached benchmark yet, we will follow up with tho= se results shortly. Additionally, we=E2=80=99ve observed that Pixel 9 behaves differently; the kernel does not perform any tag checking when the user process enables MTE. I=E2=80=99ve tested a simple kernel module that accesses kernel memory= on user ioctl, and measured the MTE perf counters on both AmpereOne and Pixel 9. Pixel 9 shows no increases in checked access counters, but AmpereOne shows proportional increases depending on the buffer size that is accessed inside the kernel module. We will keep you posted as more data becomes available. Taehyun