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This allow us to more >>> succinctly express the register set by introducing the ability to descr= ibe >>> fields and their documentation and to auto-generate the accessors. In >>> particular, this is very helpful as it does away with a lot of manual m= asks >>> and shifts. >>=20 >>=20 >> As mentioned somewhere else already I really like switching to >> register!(). Thanks! >>=20 >> Some coments below: >>=20 >>=20 >>> A future commit will eliminate HI/LO pairs once there is support for 64= bit >>> reads and writes in kernel::register. >>>=20 >>> Signed-off-by: Daniel Almeida >>> --- >>> Note that this patch depends on a rebased version of Joel's patch at [0= ]. >>>=20 >>> That version is stale, so I ended up rebasing it locally myself for the >>> purpose of developing this patch and gathering some reviews on the list= . In >>> other words, the current patch does not apply for the time being, but w= ill >>> once a v7 for Joel's series is out. >>>=20 >>> [0]: https://lore.kernel.org/rust-for-linux/20251003154748.1687160-1-jo= elagnelf@nvidia.com/ >>> --- >>> drivers/gpu/drm/tyr/driver.rs | 15 ++- >>> drivers/gpu/drm/tyr/gpu.rs | 55 ++++---- >>> drivers/gpu/drm/tyr/regs.rs | 302 ++++++++++++++++++++++++++++++++---= ------- >>> 3 files changed, 267 insertions(+), 105 deletions(-) >>>=20 >>> diff --git a/drivers/gpu/drm/tyr/driver.rs b/drivers/gpu/drm/tyr/driver= .rs >>> index 0389c558c036..8e06db5320bf 100644 >>> --- a/drivers/gpu/drm/tyr/driver.rs >>> +++ b/drivers/gpu/drm/tyr/driver.rs >>> @@ -66,19 +66,20 @@ unsafe impl Send for TyrData {} >>> unsafe impl Sync for TyrData {} >>>=20 >>> fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Resu= lt { >>> - regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; >>> + let io =3D iomem.access(dev)?; >>> + >>> + regs::GpuCommand::default() >>> + .set_command(regs::GPU_CMD_SOFT_RESET) >>> + .write(io); >>>=20 >>> // TODO: We cannot poll, as there is no support in Rust currently, = so we >>> // sleep. Change this when read_poll_timeout() is implemented in Ru= st. >>> kernel::time::delay::fsleep(time::Delta::from_millis(100)); >>>=20 >>> - if regs::GPU_IRQ_RAWSTAT.read(dev, iomem)? & regs::GPU_IRQ_RAWSTAT= _RESET_COMPLETED =3D=3D 0 { >>> + let rawstat =3D regs::GpuIrqRawstat::read(io); >>> + if !rawstat.reset_completed() { >>> dev_err!(dev, "GPU reset failed with errno\n"); >>> - dev_err!( >>> - dev, >>> - "GPU_INT_RAWSTAT is {}\n", >>> - regs::GPU_IRQ_RAWSTAT.read(dev, iomem)? >>> - ); >>> + dev_err!(dev, "GPU_INT_RAWSTAT is {}\n", u32::from(rawstat)); >>=20 >>=20 >> This is pre-existing, but printing `... INT ...` for `...IRQ...` >> register looks confusing (wrong?). > > Yeah, this needs to change indeed. > >>=20 >>=20 >>> return Err(EIO); >>> } >>> diff --git a/drivers/gpu/drm/tyr/gpu.rs b/drivers/gpu/drm/tyr/gpu.rs >>> index 6c582910dd5d..7c698fb1e36a 100644 >>> --- a/drivers/gpu/drm/tyr/gpu.rs >>> +++ b/drivers/gpu/drm/tyr/gpu.rs >>> @@ -44,34 +44,36 @@ pub(crate) struct GpuInfo { >>>=20 >>> impl GpuInfo { >>> pub(crate) fn new(dev: &Device, iomem: &Devres) -> Re= sult { >>> - let gpu_id =3D regs::GPU_ID.read(dev, iomem)?; >>> - let csf_id =3D regs::GPU_CSF_ID.read(dev, iomem)?; >>> - let gpu_rev =3D regs::GPU_REVID.read(dev, iomem)?; >>> - let core_features =3D regs::GPU_CORE_FEATURES.read(dev, iomem)= ?; >>> - let l2_features =3D regs::GPU_L2_FEATURES.read(dev, iomem)?; >>> - let tiler_features =3D regs::GPU_TILER_FEATURES.read(dev, iome= m)?; >>> - let mem_features =3D regs::GPU_MEM_FEATURES.read(dev, iomem)?; >>> - let mmu_features =3D regs::GPU_MMU_FEATURES.read(dev, iomem)?; >>> - let thread_features =3D regs::GPU_THREAD_FEATURES.read(dev, io= mem)?; >>> - let max_threads =3D regs::GPU_THREAD_MAX_THREADS.read(dev, iom= em)?; >>> - let thread_max_workgroup_size =3D regs::GPU_THREAD_MAX_WORKGRO= UP_SIZE.read(dev, iomem)?; >>> - let thread_max_barrier_size =3D regs::GPU_THREAD_MAX_BARRIER_S= IZE.read(dev, iomem)?; >>> - let coherency_features =3D regs::GPU_COHERENCY_FEATURES.read(d= ev, iomem)?; >>> - >>> - let texture_features =3D regs::GPU_TEXTURE_FEATURES0.read(dev,= iomem)?; >>> - >>> - let as_present =3D regs::GPU_AS_PRESENT.read(dev, iomem)?; >>> - >>> - let shader_present =3D u64::from(regs::GPU_SHADER_PRESENT_LO.r= ead(dev, iomem)?); >>> + let io =3D (*iomem).access(dev)?; >>> + >>> + let gpu_id =3D regs::GpuId::read(io).into(); >>> + let csf_id =3D regs::CsfId::read(io).into(); >>> + let gpu_rev =3D regs::RevIdr::read(io).into(); >>> + let core_features =3D regs::CoreFeatures::read(io).into(); >>> + let l2_features =3D regs::L2Features::read(io).into(); >>> + let tiler_features =3D regs::TilerFeatures::read(io).into(); >>> + let mem_features =3D regs::MemFeatures::read(io).into(); >>> + let mmu_features =3D regs::MmuFeatures::read(io).into(); >>> + let thread_features =3D regs::ThreadFeatures::read(io).into(); >>> + let max_threads =3D regs::ThreadMaxThreads::read(io).into(); >>> + let thread_max_workgroup_size =3D regs::ThreadMaxWorkgroupSize= ::read(io).into(); >>> + let thread_max_barrier_size =3D regs::ThreadMaxBarrierSize::re= ad(io).into(); >>> + let coherency_features =3D regs::CoherencyFeatures::read(io).i= nto(); >>=20 >>=20 >> Is there any reason why you replace the UPPERCASE register names with >> CamelCase ones? >>=20 >> I was under the impression that we want to use UPPERCASE for register >> names. Like in nova >>=20 >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/= drivers/gpu/nova-core/regs.rs > > Not really. UPPERCASE for non-const items will trigger the linter. The No= va > people chose to #[allow] this to align with OpenRM and, IIRC from the LPC > discussions, their registers are automatically generated from some intern= al > docs. > > We have only a few, we can simply convert them to CamelCase. Frankly, register names do look nicer in UPPER_CASE, especially that they'r= e in many cases, packed with acronyms. Best, Gary >>=20 >>=20 >>=20 >>> + let texture_features =3D regs::TextureFeatures::read(io, 0).in= to(); >>> + >>> + let as_present =3D regs::AsPresent::read(io).into(); >>> + >>> + let shader_present =3D u64::from(u32::from(regs::ShaderPresent= Lo::read(io))); >>> let shader_present =3D >>> - shader_present | u64::from(regs::GPU_SHADER_PRESENT_HI.rea= d(dev, iomem)?) << 32; >>> + shader_present | u64::from(u32::from(regs::ShaderPresentHi= ::read(io))) << 32;