From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Andreas Hindborg" <a.hindborg@kernel.org>
Cc: "Miguel Ojeda" <ojeda@kernel.org>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
"Danilo Krummrich" <dakr@kernel.org>,
linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org
Subject: Re: [PATCH] rust: add `CacheAligned` for easy cache line alignment of values
Date: Wed, 28 Jan 2026 23:25:55 +0900 [thread overview]
Message-ID: <DG0AIMJXPP65.1PTB9I0KQS4LI@nvidia.com> (raw)
In-Reply-To: <20260128-cache-aligned-v1-1-a4eb7c3ffd35@kernel.org>
On Wed Jan 28, 2026 at 11:05 PM JST, Andreas Hindborg wrote:
> `CacheAligned` allows to easily align values to a 64 byte boundary.
>
> An example use case is the kernel `struct spinlock`. This struct is 4 bytes
> on x86 when lockdep is not enabled. The structure is not padded to fit a
> cache line. The effect of this for `SpinLock` is that the lock variable and
> the value protected by the lock might share a cache line, depending on the
> alignment requirements of the protected value. Wrapping the value in
> `CacheAligned` to get a `SpinLock<CacheAligned<T>>` solves this problem.
>
> Signed-off-by: Andreas Hindborg <a.hindborg@samsung.com>
> ---
> Signed-off-by: Andreas Hindborg <a.hindborg@kernel.org>
> ---
> rust/kernel/cache_aligned.rs | 59 ++++++++++++++++++++++++++++++++++++++++++++
> rust/kernel/lib.rs | 2 ++
> 2 files changed, 61 insertions(+)
>
> diff --git a/rust/kernel/cache_aligned.rs b/rust/kernel/cache_aligned.rs
> new file mode 100644
> index 0000000000000..9c33b8613c077
> --- /dev/null
> +++ b/rust/kernel/cache_aligned.rs
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +use kernel::try_pin_init;
> +use pin_init::{
> + pin_data,
> + pin_init,
> + PinInit, //
> +};
> +
> +/// Wrapper type that alings content to a 64 byte cache line.
nit: s/alings/aligns
> +#[repr(align(64))]
While 64 bytes is the most common cache line size, AFAIK this is not
a universal value? Can we expose and use `L1_CACHE_BYTES` here?
next prev parent reply other threads:[~2026-01-28 14:26 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 14:05 Andreas Hindborg
2026-01-28 14:25 ` Alexandre Courbot [this message]
2026-01-28 14:41 ` Gary Guo
2026-01-28 14:45 ` Miguel Ojeda
2026-01-28 18:19 ` Andreas Hindborg
2026-01-28 14:46 ` Alice Ryhl
2026-01-28 15:05 ` Gary Guo
2026-05-18 13:41 ` Andreas Hindborg
2026-05-18 16:22 ` Gary Guo
2026-05-19 8:18 ` Andreas Hindborg
2026-05-19 10:35 ` Gary Guo
2026-05-19 11:28 ` Andreas Hindborg
2026-01-28 14:26 ` Miguel Ojeda
2026-01-28 14:34 ` Miguel Ojeda
2026-01-28 18:23 ` Andreas Hindborg
2026-01-28 18:41 ` Miguel Ojeda
2026-01-28 14:32 ` Gary Guo
2026-01-28 18:27 ` Andreas Hindborg
2026-05-19 9:16 ` Andreas Hindborg
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