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This struct is 4 by= tes >> on x86 when lockdep is not enabled. The structure is not padded to fit a >> cache line. The effect of this for `SpinLock` is that the lock variable = and >> the value protected by the lock might share a cache line, depending on t= he >> alignment requirements of the protected value. Wrapping the value in >> `CacheAligned` to get a `SpinLock>` solves this problem. >> >> Signed-off-by: Andreas Hindborg >> --- >> Signed-off-by: Andreas Hindborg >> --- >> rust/kernel/cache_aligned.rs | 59 +++++++++++++++++++++++++++++++++++++= +++++++ >> rust/kernel/lib.rs | 2 ++ >> 2 files changed, 61 insertions(+) >> >> diff --git a/rust/kernel/cache_aligned.rs b/rust/kernel/cache_aligned.rs >> new file mode 100644 >> index 0000000000000..9c33b8613c077 >> --- /dev/null >> +++ b/rust/kernel/cache_aligned.rs >> @@ -0,0 +1,59 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> + >> +use kernel::try_pin_init; >> +use pin_init::{ >> + pin_data, >> + pin_init, >> + PinInit, // >> +}; >> + >> +/// Wrapper type that alings content to a 64 byte cache line. > > nit: s/alings/aligns > >> +#[repr(align(64))] > > While 64 bytes is the most common cache line size, AFAIK this is not > a universal value? Can we expose and use `L1_CACHE_BYTES` here? Unfortunately `repr(align())` does not accept expression or macro invocatio= ns. It's still possible with code-generation, but it'll be more tricky. On all archs that we do support today, I think the value is always 64. Howe= ver it'd worth putting a FIXME or TODO (or assertion, maybe?) in case new archs= gets addded where this isn't true. Best, Gary