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Can we expose and use `L1_CACHE_BYTES` here? >>=20 >> On all archs that we do support today, I think the value is always 64. H= owever >> it'd worth putting a FIXME or TODO (or assertion, maybe?) in case new ar= chs gets >> addded where this isn't true. > > Are you sure? From Tokio: > >> Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pa= irs of 64-byte cache >> lines at a time, so we have to align to 128 bytes rather than 64. A cache line is still 64B, even if a prefetcher might pull in multiple cach= e lines. The hardware prefetcher usually only engage when a sequential access patter= n is discovered. So if you're doing array access with increasing index, it would engage and pull in next cache line; however if you are performing random ac= cess (e.g. following a link list), it would not engage, as otherwise you're effectively having half the number of cache lines available in your L1 cach= e. If the software need to fight the hardware prefetcher in general (where the= re's no regular seqential access pattern) by spreading things further apart in memory, it means that the hardware prefetcher has failed its task and is a = bad design :) >> >> Sources: >> - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/6= 4-ia-32-architectures-optimization-manual.pdf >> - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e= 73bbb9fbb/folly/lang/Align.h#L107 >> >> ARM's big.LITTLE architecture has asymmetric cores and "big" cores have = 128-byte cache line size. >> >> Sources: >> - https://www.mono-project.com/news/2016/09/12/arm64-icache/ arch/arm64/include/asm/cache.h defines L1_CACHE_BYTES as 64. >> >> powerpc64 has 128-byte cache line size. >> >> Sources: >> - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489= d4d2/src/internal/cpu/cpu_ppc64x.go#L9 There's no PPC support today in kernel Rust today. Best, Gary > > https://github.com/tokio-rs/tokio/blob/master/tokio/src/util/cacheline.rs= #L85