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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8dbf183cbesm224977466b.38.2026.01.29.00.32.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 29 Jan 2026 00:32:49 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 29 Jan 2026 09:32:49 +0100 Message-Id: Cc: "Bjorn Andersson" , "Linus Walleij" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller From: "Luca Weiss" To: "Dmitry Baryshkov" , "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> <20260128-sm6350-lpi-tlmm-v1-4-36583f2a2a2a@fairphone.com> In-Reply-To: On Wed Jan 28, 2026 at 11:16 PM CET, Dmitry Baryshkov wrote: > On Wed, Jan 28, 2026 at 01:26:52PM +0100, Luca Weiss wrote: >> Add LPASS LPI pinctrl node required for audio functionality on SM6350. >>=20 >> Signed-off-by: Luca Weiss >> --- >> arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 +++++++++++++++++++++++++++++= +++++++ >> 1 file changed, 66 insertions(+) >>=20 >> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/= qcom/sm6350.dtsi >> index 9f9b9f9af0da..b1fb6c812da7 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >> @@ -1448,6 +1448,72 @@ compute-cb@5 { >> }; >> }; >> =20 >> + lpass_tlmm: pinctrl@33c0000 { >> + compatible =3D "qcom,sm6350-lpass-lpi-pinctrl"; >> + reg =3D <0x0 0x033c0000 0x0 0x20000>, >> + <0x0 0x03550000 0x0 0x10000>; >> + gpio-controller; >> + #gpio-cells =3D <2>; >> + gpio-ranges =3D <&lpass_tlmm 0 0 15>; >> + >> + clocks =3D <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_= NO>, >> + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >> + clock-names =3D "core", >> + "audio"; >> + >> + i2s1_active: i2s1-active-state { >> + clk-pins { >> + pins =3D "gpio6"; >> + function =3D "i2s1_clk"; >> + drive-strength =3D <8>; >> + bias-disable; >> + output-high; > > This looks suspicious for the clock pin. > >> + }; >> + >> + ws-pins { >> + pins =3D "gpio7"; >> + function =3D "i2s1_ws"; >> + drive-strength =3D <8>; >> + bias-disable; >> + output-high; > > The same > >> + }; >> + >> + data-pins { >> + pins =3D "gpio8", "gpio9"; >> + function =3D "i2s1_data"; >> + drive-strength =3D <8>; >> + bias-disable; >> + output-high; > > And here. I've taken this pinctrl from downstream lagoon-lpi.dtsi. There the active config for these pins have "output-high;" set. And fwiw this pinctrl works fine at runtime for driving the speaker. Regards Luca > >> + }; >> + }; >> + >> + i2s1_sleep: i2s1-sleep-state { >> + clk-pins { >> + pins =3D "gpio6"; >> + function =3D "i2s1_clk"; >> + drive-strength =3D <2>; >> + bias-pull-down; >> + input-enable; >> + }; >> + >> + ws-pins { >> + pins =3D "gpio7"; >> + function =3D "i2s1_ws"; >> + drive-strength =3D <2>; >> + bias-pull-down; >> + input-enable; >> + }; >> + >> + data-pins { >> + pins =3D "gpio8", "gpio9"; >> + function =3D "i2s1_data"; >> + drive-strength =3D <2>; >> + bias-pull-down; >> + input-enable; >> + }; >> + }; >> + }; >> + >> gpu: gpu@3d00000 { >> compatible =3D "qcom,adreno-619.0", "qcom,adreno"; >> reg =3D <0x0 0x03d00000 0x0 0x40000>, >>=20 >> --=20 >> 2.52.0 >>=20