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b=Tk+f1G/08F4dkIdlk9Om6rT+S7R8UogSUbLTe+d3eUM3fXadkHCBDojGo/wx+9Pciy3UI2Fs7u+oTS+cE6XrI5TmazEiyg9FK3h/zK21QnIAJV/9AVsxz0tq+YHJRpLNVuGafMIuJbWZXMgSL96xX/axHNBnFxzxhdhdTeJkexRAkNQXQoPN08XKiRKXtZnF0F6eKzZEPEzHSgDrKFsqajevu8JJxJzrazvBZX1idi8wrbe071buJIPyZvDK0QtnXftyEx20TzHwouSKs6c0vNfC/rZkY0JWaj7LdNe1sjLWDXlRukIBp5wzynE4d8gJbopLUKeXXiCoYcsr7nKGmA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB3997.namprd12.prod.outlook.com (2603:10b6:208:161::11) by IA0PR12MB7580.namprd12.prod.outlook.com (2603:10b6:208:43b::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9564.10; Fri, 30 Jan 2026 06:55:15 +0000 Received: from MN2PR12MB3997.namprd12.prod.outlook.com ([fe80::73c6:e479:9b75:b2cf]) by MN2PR12MB3997.namprd12.prod.outlook.com ([fe80::73c6:e479:9b75:b2cf%5]) with mapi id 15.20.9564.008; Fri, 30 Jan 2026 06:55:09 +0000 Content-Type: text/plain; charset=UTF-8 Date: Fri, 30 Jan 2026 15:55:03 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "Daniel Almeida" , "Miguel Ojeda" , "Boqun Feng" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "Yury Norov" , "John Hubbard" , "Alistair Popple" , "Joel Fernandes" , "Timur Tabi" , "Edwin Peer" , "Eliot Courtney" , "Dirk Behme" , "Steven Price" , , Subject: Re: [PATCH v4 5/7] rust: io: add `register!` macro From: "Alexandre Courbot" To: "Gary Guo" Content-Transfer-Encoding: quoted-printable References: <20260128-register-v4-0-aee3a33d9649@nvidia.com> <20260128-register-v4-5-aee3a33d9649@nvidia.com> In-Reply-To: X-ClientProxiedBy: OSTPR01CA0043.jpnprd01.prod.outlook.com (2603:1096:604:21b::20) To MN2PR12MB3997.namprd12.prod.outlook.com (2603:10b6:208:161::11) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN2PR12MB3997:EE_|IA0PR12MB7580:EE_ X-MS-Office365-Filtering-Correlation-Id: 28b04390-2eef-43c1-5881-08de5fcc80f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|10070799003; 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>>>> pub mod poll; >>>> +pub mod register; >>>> pub mod resource; >>>> =20 >>>> pub use resource::Resource; >>>> diff --git a/rust/kernel/io/register.rs b/rust/kernel/io/register.rs >>>> new file mode 100644 >>>> index 000000000000..fc85dcd1f09a >>>> --- /dev/null >>>> +++ b/rust/kernel/io/register.rs >>>> @@ -0,0 +1,1287 @@ >>>> +// SPDX-License-Identifier: GPL-2.0 >>>> + >>>> +//! A macro to define register layout and accessors. >>>> +//! >>>> +//! A single register typically includes several fields, which are ac= cessed through a combination >>>> +//! of bit-shift and mask operations that introduce a class of potent= ial mistakes, notably because >>>> +//! not all possible field values are necessarily valid. >>>> +//! >>>> +//! The [`register!`] macro in this module provides an intuitive and = readable syntax for defining a >>>> +//! dedicated type for each register. Each such type comes with its o= wn field accessors that can >>>> +//! return an error if a field's value is invalid. >>>> +//! >>>> +//! [`register!`]: kernel::register! >>>> + >>>> +use core::ops::Deref; >>>> + >>>> +use crate::io::{ >>>> + IoCapable, >>>> + IoKnownSize, // >>>> +}; >>>> + >>>> +/// Trait providing a base address to be added to the offset of a rel= ative register to obtain >>>> +/// its actual offset. >>>> +/// >>>> +/// The `T` generic argument is used to distinguish which base to use= , in case a type provides >>>> +/// several bases. It is given to the `register!` macro to restrict t= he use of the register to >>>> +/// implementors of this particular variant. >>>> +pub trait RegisterBase { >>>> + /// Base address to which register offsets are added. >>>> + const BASE: usize; >>>> +} >>>> + >>>> +/// Trait providing I/O read/write operations for register storage ty= pes. >>>> +/// >>>> +/// This trait is implemented for all integer types on which I/O can = be performed, allowing the >>>> +/// `register!` macro to generate appropriate I/O accessor methods ba= sed on the register's storage >>>> +/// type. >>>> +pub trait RegisterIo: Sized { >>> >>> Is this trait intended for public usage or just internal detail of `reg= ister!()` >>> macro? >>> >>> If it's the former, then we should probably just put the method into `I= oCapable` >>> and allow generic-read in Io. If it's the latter, let's `#[doc(hidden)]= ` this so >>> it won't get abused. >> >> It is an internal detail of `register!()` and not supposed to be used by= anyone >> else. >> >>> >>>> + /// Read a value from the given offset in the I/O region. >>>> + fn read(io: &T, offset: usize) -> Self >>>> + where >>>> + T: Deref, >>>> + I: IoKnownSize + IoCapable; >>> >>> I think generally `Deref` bound shouldn't be exposed to user. What smar= t >>> pointers are involved here, and can we implement forwarding impls of `I= o`? >> >> Removing the requirement for `Deref` in the `RegisterIo` trait is simple= - we >> can just call `Deref` in the register IO accessors. > > The issue with `Deref` bound here is that now you *require* a level of > indirection. If something implements `Io` directly, you cannot use it wit= h the > method. While `&Bar` is accepted, `&Mmio` is not because `Mmio` is a dire= ct > implementor of `Io` and not deref to it. > > A `Deref` bound also does not help if, say, a type is `Arc` which ne= eds two > level of dereffing before it is Io. For consistency I think it's best to = avoid > `Deref` call all together Do you mean that `Bar` should implement `Io`, `IoKnownSize`, and all the required `IoCapable`s? That's a lot of boilerplate I'm afraid, and that would need to be repeated for all other I/O proxy types. No, I'm starting to believe that the fundamental issue is that the register interface does its I/O backwards, and that design issue is only exacerbated by the recent I/O redesign. I.e. instead of doing regs::NV_PMC_BOOT_0::read(bar); We should really do bar.read_reg::(); Because that way we can use deref coercion. That's quite a big redesign though, which means I don't believe `register!` can make it this cycle... I'll give it a try though. >>>> + $vis struct $name($storage); >>>> + >>>> + #[allow(dead_code)] >>>> + impl $name { >>>> + /// Creates a bitfield from a raw value. >>>> + $vis const fn from_raw(value: $storage) -> Self { >>>> + Self(value) >>>> + } >>>> + >>>> + /// Creates a zeroed bitfield value. >>>> + /// >>>> + /// This is a const alternative to the `Zeroable::zeroed(= )` trait method. >>>> + $vis const fn zeroed() -> Self { >>>> + Self(0) >>>> + } >>> >>> All types that impl `Zeroable` automatically have the `::zeroed()` fn p= rovided >>> via the trait. >> >> Yes, but that method from the trait cannot be used in const context, and >> `zeroed` is the starting point for building register values from scratch= (and >> thus constant values). > > `pin_init:::zeroed()` is a const function. Ah, I thought about using `Zeroable::zeroed()` at first, but indeed we can use the function instead. Strangely though, I expected to be able to do const V: BOOT_0 =3D pin_init::zeroed() and have the compiler infer the generic type, but for some reason I have to specify it explicitly: const V: BOOT_0 =3D pin_init::zeroed::() Not a big deal, but a const method would reduce this to=20 const V: BOOT_0 =3D BOOT_0::zeroed() (for variables `let v: BOOT_0 =3D pin_init::zeroed()` works fine.)