From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140391A294 for ; Mon, 9 Feb 2026 10:31:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633090; cv=none; b=E01YFMizOqD5MWE37R6/OocgF8UUCqkD/eHWAjM5V+EcEy5pZ74tcJTL+sezdCHlUo0XaRgS01o5fteuLc5DLOD+uk+w4dmMJxB4vZBjJcxvl3DaydDtirOJSwxNeXSrQwDYTnOM+nv2zzk7rErzOWEtEGepd+/4nPjRhjgKHKg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770633090; c=relaxed/simple; bh=TwBzdsVRrRybLDrsjk53rOG84qihoqSrcyNa1p9EUdI=; h=Mime-Version:Content-Type:Date:Message-Id:Subject:Cc:From:To: References:In-Reply-To; b=qZmkndAsYySJu4Fk7/XW4KB2WO9+Jt5heKD5Z3HX9Lhyz6tX9H/2XV/ejYrVAbm1OdSTFwNWHG+tdZ9fEx8gU0Iq13xcZrIlM7+8Uz+KP83oKnKAbMk8ObKMbOHb+Byy4y6c1qlhmauELWqcym8rxSennBJC+HMacLLiyGY+zAY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bOJ1/z/c; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bOJ1/z/c" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2B76EC116C6; Mon, 9 Feb 2026 10:31:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1770633089; bh=TwBzdsVRrRybLDrsjk53rOG84qihoqSrcyNa1p9EUdI=; h=Date:Subject:Cc:From:To:References:In-Reply-To:From; b=bOJ1/z/cYdv86jCNXgWrawsbiYDjfW3JigQma1OyEPFuj9u7q0lgq0m5xPzm01TYQ i9FcHzQ+F6xUKVXahi2LydOQZI1n8ppFRxUwCDqSkOJNN9JK9w4MK1r5NV6YCkcHIV 0PC9YZmcx5dKU6LZh+XI4vCZH+9xK2udQQJQZvRsy8T7HfMFoZ8NqXRfjj0GvETocN aCUMx3/tvc32/dPXehz/Hm+foAp129A8onIgz7ss4CpNA9b7sAh3y7XD/CapdErCqJ keb/mHKDngvAAufCsGRppBhjEYqBrEZfGYbr7cQ1wFbU5FNpTTh1xwGtJqCfm8qvCm Ci5gEve6qgXLg== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: multipart/signed; boundary=3a0cbeae8d59140c80745bc1636a288489d9709fcbb5063fa72cad364e60; micalg=pgp-sha384; protocol="application/pgp-signature" Date: Mon, 09 Feb 2026 11:31:25 +0100 Message-Id: Subject: Re: [PATCH] mtd: spi-nor: swp: check SR_TB flag when getting tb_mask Cc: "Tudor Ambarus" , "Pratyush Yadav" , "Miquel Raynal" , "Richard Weinberger" , "Vignesh Raghavendra" , From: "Michael Walle" To: "Shiji Yang" , X-Mailer: aerc 0.20.0 References: In-Reply-To: --3a0cbeae8d59140c80745bc1636a288489d9709fcbb5063fa72cad364e60 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 On Wed Jan 28, 2026 at 1:42 PM CET, Shiji Yang wrote: > When the chip does not support top/bottom block protect, the tb_mask > must be set to 0, otherwise SR1 bit5 will be unexpectedly modified. > > Signed-off-by: Shiji Yang It goes all the way back to the very first commit.. Fixes: 3dd8012a8eeb ("mtd: spi-nor: add TB (Top/Bottom) protect support") Reviewed-by: Michael Walle -michael --3a0cbeae8d59140c80745bc1636a288489d9709fcbb5063fa72cad364e60 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKgEABMJADAWIQTIVZIcOo5wfU/AngkSJzzuPgIf+AUCaYm3fRIcbXdhbGxlQGtl cm5lbC5vcmcACgkQEic87j4CH/iKpAF8CDyRUYovF37XMeqHzzqdW33hta7ep+Ky H/Oi/IwS07OPNZyBw7i+tlgl2ryxNHY8AYDCmvEf3rLCrHZX0UybMS4XmHP5/nWJ qS8iTw4CtYqq5P5/c4EjUC0l4LsIaEsB3ik= =JGHc -----END PGP SIGNATURE----- --3a0cbeae8d59140c80745bc1636a288489d9709fcbb5063fa72cad364e60--