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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b942ef8ad0fsm46007966b.19.2026.03.06.02.37.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Mar 2026 02:37:08 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 06 Mar 2026 11:37:08 +0100 Message-Id: To: "Konrad Dybcio" , "Krzysztof Kozlowski" , "Luca Weiss" , "Taniya Das" Cc: "Georgi Djakov" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , Subject: Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path From: "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260116-milos-camcc-icc-v1-0-400b7fcd156a@fairphone.com> <20260116-milos-camcc-icc-v1-2-400b7fcd156a@fairphone.com> <20260117-efficient-fractal-sloth-aaf7c2@quoll> <59d9f7ff-4111-4304-a76c-40f4000545f5@oss.qualcomm.com> <9f8619d4-43ac-4bc0-9598-c498d59a27b8@oss.qualcomm.com> In-Reply-To: <9f8619d4-43ac-4bc0-9598-c498d59a27b8@oss.qualcomm.com> Hi Taniya, On Mon Jan 19, 2026 at 11:28 AM CET, Konrad Dybcio wrote: > On 1/19/26 11:20 AM, Konrad Dybcio wrote: >> On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote: >>> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote: >>>> Document an interconnect path for camcc that's required to enable >>>> the CAMSS_TOP_GDSC power domain. >>> >>> I find it confusing. Enabling GDSC power domains is done via power >>> domains, not via interconnects. Do not represent power domains as >>> interconnects, it's something completely different. >>=20 >> The name of the power domains is CAMSS_TOP_GDSC (seems you misread) >>=20 >> For the power domain to successfully turn on, the MNoC needs to be >> turned on (empirical evidence). The way to do it is to request a >> nonzero vote on this interconnect path >>=20 >> (presumably because the GDSC or its invisible providers require >> something connected over that bus to carry out their enable sequences). Do you have any details you can share for this discussion? Regards Luca