Re: [PATCH 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC

["Shuwei Wu" <shuwei.wu@mailbox.org>]

Hi Samuel,

On Mon Mar 9, 2026 at 1:59 AM CST, Samuel Holland wrote:
> Hi Shuwei,
>
> On 2026-03-07 11:17 PM, Shuwei Wu wrote:
>> Add Operating Performance Points (OPP) tables and CPU clock properties
>> for the two clusters in the SpacemiT K1 SoC.
>> 
>> Also assign the CPU power supply (cpu-supply) for the Banana Pi BPI-F3
>> board to fully enable CPU DVFS.
>> 
>> Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
>> ---
>>  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 34 +++++++++-
>>  arch/riscv/boot/dts/spacemit/k1.dtsi            | 86 +++++++++++++++++++++++++
>>  2 files changed, 119 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> index 444c3b1e6f44..b87bf9d51cb1 100644
>> --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
>> @@ -86,6 +86,38 @@ &combo_phy {
>>  	status = "okay";
>>  };
>>  
>> +&cpu_0 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_1 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_2 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_3 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_4 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_5 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_6 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>> +&cpu_7 {
>> +	cpu-supply = <&buck1_3v45>;
>> +};
>> +
>>  &emmc {
>>  	bus-width = <8>;
>>  	mmc-hs400-1_8v;
>> @@ -201,7 +233,7 @@ pmic@41 {
>>  		dldoin2-supply = <&buck5>;
>>  
>>  		regulators {
>> -			buck1 {
>> +			buck1_3v45: buck1 {
>>  				regulator-min-microvolt = <500000>;
>>  				regulator-max-microvolt = <3450000>;
>>  				regulator-ramp-delay = <5000>;
>> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> index 529ec68e9c23..5c7bb5d85fc0 100644
>> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
>> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
>> @@ -54,6 +54,8 @@ cpu_0: cpu@0 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <0>;
>> +			clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
>> +			operating-points-v2 = <&cluster0_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -84,6 +86,8 @@ cpu_1: cpu@1 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <1>;
>> +			clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
>> +			operating-points-v2 = <&cluster0_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -114,6 +118,8 @@ cpu_2: cpu@2 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <2>;
>> +			clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
>> +			operating-points-v2 = <&cluster0_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -144,6 +150,8 @@ cpu_3: cpu@3 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <3>;
>> +			clocks = <&syscon_apmu CLK_CPU_C0_CORE>;
>> +			operating-points-v2 = <&cluster0_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -174,6 +182,8 @@ cpu_4: cpu@4 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <4>;
>> +			clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
>> +			operating-points-v2 = <&cluster1_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -204,6 +214,8 @@ cpu_5: cpu@5 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <5>;
>> +			clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
>> +			operating-points-v2 = <&cluster1_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -234,6 +246,8 @@ cpu_6: cpu@6 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <6>;
>> +			clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
>> +			operating-points-v2 = <&cluster1_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -264,6 +278,8 @@ cpu_7: cpu@7 {
>>  			compatible = "spacemit,x60", "riscv";
>>  			device_type = "cpu";
>>  			reg = <7>;
>> +			clocks = <&syscon_apmu CLK_CPU_C1_CORE>;
>> +			operating-points-v2 = <&cluster1_opp_table>;
>>  			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
>>  			riscv,isa-base = "rv64i";
>>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
>> @@ -339,6 +355,76 @@ osc_32k: clock-32k {
>>  		};
>>  	};
>>  
>> +	cluster0_opp_table: opp-table-cluster0 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-614400000 {
>> +			opp-hz = /bits/ 64 <614400000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-819000000 {
>> +			opp-hz = /bits/ 64 <819000000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1000000000 {
>> +			opp-hz = /bits/ 64 <1000000000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1228800000 {
>> +			opp-hz = /bits/ 64 <1228800000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1600000000 {
>> +			opp-hz = /bits/ 64 <1600000000>;
>> +			opp-microvolt = <1050000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +	};
>> +
>> +	cluster1_opp_table: opp-table-cluster1 {
>> +		compatible = "operating-points-v2";
>> +		opp-shared;
>> +
>> +		opp-614400000 {
>> +			opp-hz = /bits/ 64 <614400000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-819000000 {
>> +			opp-hz = /bits/ 64 <819000000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1000000000 {
>> +			opp-hz = /bits/ 64 <1000000000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1228800000 {
>> +			opp-hz = /bits/ 64 <1228800000>;
>> +			opp-microvolt = <950000>;
>> +			clock-latency-ns = <200000>;
>> +		};
>> +
>> +		opp-1600000000 {
>> +			opp-hz = /bits/ 64 <1600000000>;
>> +			opp-microvolt = <1050000>;
>> +			clock-latency-ns = <200000>;
>
> What is the initial voltage set by firmware before Linux boots? If it is 1.05V,
> this is fine, but if the default is 950mV, then you cannot enable the OPP table
> in the SoC .dtsi file. Boards other than the BananaPi F3 are missing the
> cpu-supply property, so they won't raise the CPU voltage before switching to the
> higher frequency. The usual solution is to put the OPP table (or at least the
> OPPs that require a higher voltage) in a separate .dtsi file, and only include
> that file from boards that provide the cpu-supply.
>
> Regards,
> Samuel

Thanks for the suggestion!
I confirmed the firmware sets the initial voltage to 1.05V at the default boot
frequency before any scaling occurs:

~ # cat /sys/class/regulator/regulator.4/name
buck1
~ # cat /sys/class/regulator/regulator.4/microvolts
1050000

But I agree that moving the OPP tables to a separate .dtsi is a much safer
and more robust approach for boards without cpu-supply.
I will implement this in v2.

Best regards,
-- 
Shuwei Wu