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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-667ac611b88sm59632a12.0.2026.03.17.07.50.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2026 07:50:08 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 17 Mar 2026 15:50:07 +0100 Message-Id: To: "Konrad Dybcio" , "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Tengfei Fan" , "Dmitry Baryshkov" , "Jingyi Wang" , "Luca Weiss" , "Vinod Koul" , "Dmitry Baryshkov" , "Sai Prakash Ranjan" , "Neil Armstrong" , "Abel Vesa" , "Raviteja Laggyshetty" , "Melody Olvera" , "Taniya Das" Cc: , , , "Jishnu Prakash" , "Konrad Dybcio" Subject: Re: [PATCH 2/6] arm64: dts: qcom: milos: Fix GIC_ITS range length From: "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260317-topic-its_range_fixup-v1-0-49be8076adb1@oss.qualcomm.com> <20260317-topic-its_range_fixup-v1-2-49be8076adb1@oss.qualcomm.com> In-Reply-To: <20260317-topic-its_range_fixup-v1-2-49be8076adb1@oss.qualcomm.com> On Tue Mar 17, 2026 at 3:41 PM CET, Konrad Dybcio wrote: > From: Konrad Dybcio > > Currently, the GITS_SGIR register is cut off. Fix it up. > > Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") > Signed-off-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/milos.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qc= om/milos.dtsi > index e1a51d43943f..084be5316e0d 100644 > --- a/arch/arm64/boot/dts/qcom/milos.dtsi > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi > @@ -1911,7 +1911,7 @@ ppi_cluster1: interrupt-partition-1 { > =20 > gic_its: msi-controller@17140000 { > compatible =3D "arm,gic-v3-its"; > - reg =3D <0x0 0x17140000 0x0 0x20000>; > + reg =3D <0x0 0x17140000 0x0 0x40000>; The .FLAT doesn't make it super obvious what the size should be, but yes, GITS0_SGIR would be outside the range with 0x20000, and 0x40000 looks sane given at 0x1718_0000 the next register after GITS0_SGIR is located. Reviewed-by: Luca Weiss > =20 > msi-controller; > #msi-cells =3D <1>;