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quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 19 Mar 2026 23:18:08 +0900 Message-Id: From: "Alexandre Courbot" To: "Eliot Courtney" Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Miguel Ojeda" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Trevor Gross" , "John Hubbard" , "Alistair Popple" , "Joel Fernandes" , "Timur Tabi" , "Zhi Wang" , , , , , Subject: Re: [PATCH 1/8] gpu: nova-core: convert PMC registers to kernel register macro References: <20260318-b4-nova-register-v1-0-22a358aa4c63@nvidia.com> <20260318-b4-nova-register-v1-1-22a358aa4c63@nvidia.com> In-Reply-To: X-ClientProxiedBy: TY4P286CA0053.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:36e::18) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: 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LNHExBVs/qV/hyxatlgZwE7hsaLe7eMEzRqF9o76ivZuiJQZzvoye+KvhOtR8aD9ENGwfwUmQxKA6IJEI8cNvw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9198 On Thu Mar 19, 2026 at 11:16 AM JST, Eliot Courtney wrote: > On Thu Mar 19, 2026 at 11:07 AM JST, Alexandre Courbot wrote: >> On Thu Mar 19, 2026 at 10:42 AM JST, Eliot Courtney wrote: >>> On Wed Mar 18, 2026 at 5:05 PM JST, Alexandre Courbot wrote: >>>> Convert all PMC registers to use the kernel's register macro and updat= e >>>> the code accordingly. >>>> >>>> nova-core's registers have some constant properties (like a 32-bit siz= e >>>> and a crate visibility), so introduce the `nv_reg` macro to shorten >>>> their declaration. >>>> >>>> Signed-off-by: Alexandre Courbot >>>> --- >>>> drivers/gpu/nova-core/falcon.rs | 7 ++-- >>>> drivers/gpu/nova-core/gpu.rs | 37 ++++++++++----------- >>>> drivers/gpu/nova-core/regs.rs | 73 +++++++++++++++++++++++++++++++-= --------- >>>> 3 files changed, 78 insertions(+), 39 deletions(-) >>>> >>>> diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/f= alcon.rs >>>> index 7097a206ec3c..4721865f59d9 100644 >>>> --- a/drivers/gpu/nova-core/falcon.rs >>>> +++ b/drivers/gpu/nova-core/falcon.rs >>>> @@ -13,7 +13,10 @@ >>>> DmaAddress, >>>> DmaMask, // >>>> }, >>>> - io::poll::read_poll_timeout, >>>> + io::{ >>>> + poll::read_poll_timeout, // >>>> + Io, >>>> + }, >>> >>> nit: // should be on the last import? >> >> It should, thanks. >> >>> >>>> prelude::*, >>>> sync::aref::ARef, >>>> time::Delta, >>>> @@ -532,7 +535,7 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result { >>>> self.hal.reset_wait_mem_scrubbing(bar)?; >>>> =20 >>>> regs::NV_PFALCON_FALCON_RM::default() >>>> - .set_value(regs::NV_PMC_BOOT_0::read(bar).into()) >>>> + .set_value(bar.read(regs::NV_PMC_BOOT_0).into()) >>>> .write(bar, &E::ID); >>>> =20 >>>> Ok(()) >>>> diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.= rs >>>> index 8579d632e717..d81abc7de3d7 100644 >>>> --- a/drivers/gpu/nova-core/gpu.rs >>>> +++ b/drivers/gpu/nova-core/gpu.rs >>>> @@ -4,6 +4,8 @@ >>>> device, >>>> devres::Devres, >>>> fmt, >>>> + io::Io, >>>> + num::Bounded, >>>> pci, >>>> prelude::*, >>>> sync::Arc, // >>>> @@ -129,24 +131,18 @@ fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt= ::Result { >>>> } >>>> =20 >>>> /// Enum representation of the GPU generation. >>>> -/// >>>> -/// TODO: remove the `Default` trait implementation, and the `#[defau= lt]` >>>> -/// attribute, once the register!() macro (which creates Architecture= items) no >>>> -/// longer requires it for read-only fields. >>>> -#[derive(fmt::Debug, Default, Copy, Clone)] >>>> -#[repr(u8)] >>>> +#[derive(fmt::Debug, Copy, Clone)] >>>> pub(crate) enum Architecture { >>>> - #[default] >>>> Turing =3D 0x16, >>>> Ampere =3D 0x17, >>>> Ada =3D 0x19, >>>> } >>>> =20 >>>> -impl TryFrom for Architecture { >>>> +impl TryFrom> for Architecture { >>>> type Error =3D Error; >>>> =20 >>>> - fn try_from(value: u8) -> Result { >>>> - match value { >>>> + fn try_from(value: Bounded) -> Result { >>>> + match u8::from(value) { >>>> 0x16 =3D> Ok(Self::Turing), >>>> 0x17 =3D> Ok(Self::Ampere), >>>> 0x19 =3D> Ok(Self::Ada), >>>> @@ -155,23 +151,26 @@ fn try_from(value: u8) -> Result { >>>> } >>>> } >>>> =20 >>>> -impl From for u8 { >>>> +impl From for Bounded { >>>> fn from(value: Architecture) -> Self { >>>> - // CAST: `Architecture` is `repr(u8)`, so this cast is always= lossless. >>>> - value as u8 >>>> + match value { >>>> + Architecture::Turing =3D> Bounded::::new::<0x16>(= ), >>>> + Architecture::Ampere =3D> Bounded::::new::<0x17>(= ), >>>> + Architecture::Ada =3D> Bounded::::new::<0x19>(), >>>> + } >>>> } >>>> } >>>> =20 >>>> pub(crate) struct Revision { >>>> - major: u8, >>>> - minor: u8, >>>> + major: Bounded, >>>> + minor: Bounded, >>>> } >>>> =20 >>>> impl From for Revision { >>>> fn from(boot0: regs::NV_PMC_BOOT_42) -> Self { >>>> Self { >>>> - major: boot0.major_revision(), >>>> - minor: boot0.minor_revision(), >>>> + major: boot0.major_revision().cast(), >>>> + minor: boot0.minor_revision().cast(), >>>> } >>>> } >>>> } >>>> @@ -208,13 +207,13 @@ fn new(dev: &device::Device, bar: &Bar0) -> Resu= lt { >>>> // from an earlier (pre-Fermi) era, and then using boot42= to precisely identify the GPU. >>>> // Somewhere in the Rubin timeframe, boot0 will no longer= have space to add new GPU IDs. >>>> =20 >>>> - let boot0 =3D regs::NV_PMC_BOOT_0::read(bar); >>>> + let boot0 =3D bar.read(regs::NV_PMC_BOOT_0); >>>> =20 >>>> if boot0.is_older_than_fermi() { >>>> return Err(ENODEV); >>>> } >>>> =20 >>>> - let boot42 =3D regs::NV_PMC_BOOT_42::read(bar); >>>> + let boot42 =3D bar.read(regs::NV_PMC_BOOT_42); >>>> Spec::try_from(boot42).inspect_err(|_| { >>>> dev_err!(dev, "Unsupported chipset: {}\n", boot42); >>>> }) >>>> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/reg= s.rs >>>> index 53f412f0ca32..62c2065e63ef 100644 >>>> --- a/drivers/gpu/nova-core/regs.rs >>>> +++ b/drivers/gpu/nova-core/regs.rs >>>> @@ -35,20 +35,64 @@ >>>> num::FromSafeCast, >>>> }; >>>> =20 >>>> +// All nova-core registers are 32-bit and `pub(crate)`. Wrap the `reg= ister!` macro to avoid >>>> +// repeating this information for every register. >>>> +macro_rules! nv_reg { >>>> + ( >>>> + $( >>>> + $(#[$attr:meta])* $name:ident $([ $size:expr $(, stride = =3D $stride:expr)? ])? >>>> + $(@ $offset:literal)? >>>> + $(@ $base:ident + $base_offset:literal)? >>>> + $(=3D> $alias:ident $(+ $alias_offset:ident)? $([$ali= as_idx:expr])? )? >>>> + $(, $comment:literal)? { $($fields:tt)* } >>>> + )* >>>> + )=3D> { >>>> + $( >>>> + ::kernel::io::register!( >>>> + @reg $(#[$attr])* pub(crate) $name(u32) $([$size $(, stri= de =3D $stride)?])? >>>> + $(@ $offset)? >>>> + $(@ $base + $base_offset)? >>>> + $(=3D> $alias $(+ $alias_offset)? $([$alias_idx])? )? >>>> + $(, $comment)? { $($fields)* } >>>> + ); >>>> + )* >>>> + }; >>>> +} >>>> + >>> >>> Is it really worth introducing this macro to save pub(crate) and (u32)? >>> Are we definitely going to always be using pub(crate) and u32? >> >> So far we are. I'm not particularly passionate about it, but I think >> it's nice not having to repeat ourselves (and potentially introduce >> typos). > > One downside is that the nested macros make it harder to check the > implementation since you have to go to this definition, then to the > register macro definition if you want to check something. And I also > feel like I need to read this intermediate macro definition to see if > it's doing anything special if I run into some error. > > Personally I would probably go with just using the register macro > directly, and then we can tighten the visibility later if it's useful > without having to change all of these. But not a super strong opinion, > so up to you. Just doesn't feel like it saves us that much in typing the > extra tens of characters. IIRC Danilo also had reservations about `nv_reg` when we chatted about it - I'll remove it from the next revision to see what it looks like.