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charset=UTF-8 Date: Sat, 28 Mar 2026 22:03:13 +0900 Message-Id: Cc: "Eliot Courtney" , "Danilo Krummrich" , "Abdiel Janulgue" , "Daniel Almeida" , "Robin Murphy" , "Andreas Hindborg" , "Miguel Ojeda" , "Boqun Feng" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "John Hubbard" , "Alistair Popple" , "Joel Fernandes" , "Timur Tabi" , "Zhi Wang" , , , Subject: Re: [PATCH 4/7] gpu: nova-core: falcon: use dma::Coherent From: "Alexandre Courbot" To: "Gary Guo" References: <20260321-b4-nova-dma-removal-v1-0-5cf18a75ff64@nvidia.com> <20260321-b4-nova-dma-removal-v1-4-5cf18a75ff64@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCPR01CA0156.jpnprd01.prod.outlook.com (2603:1096:400:2b1::16) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LVUPR12MB999160:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f6ae391-e1b5-4cb0-61b8-08de8cca613d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|366016|10070799003|56012099003|22082099003|18002099003; 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>>>> =20 >>>> use crate::{ >>>> - dma::DmaObject, >>>> driver::Bar0, >>>> falcon::hal::LoadMethod, >>>> gpu::Chipset, >>>> @@ -636,7 +636,7 @@ pub(crate) fn pio_load + FalconPioLoadable>( >>>> fn dma_wr( >>>> &self, >>>> bar: &Bar0, >>>> - dma_obj: &DmaObject, >>>> + dma_obj: &Coherent<[u8]>, >>>> target_mem: FalconMem, >>>> load_offsets: FalconDmaLoadTarget, >>>> ) -> Result { >>>> @@ -740,7 +740,7 @@ fn dma_load + Falc= onDmaLoadable>( >>>> fw: &F, >>>> ) -> Result { >>>> // Create DMA object with firmware content as the source of t= he DMA engine. >>>> - let dma_obj =3D DmaObject::from_data(dev, fw.as_slice())?; >>>> + let dma_obj =3D Coherent::from_slice(dev, fw.as_slice(), GFP_= KERNEL)?; >>> >>> Is it guaranteed that fw.as_slice() is a multiple of 256 in size? >>> In `dma_wr` it breaks this up into 256 byte transfers. Since this >>> no longer pads out to a page boundary, it means that it could now error >>> (around "DMA transfer goes beyond range of DMA object") if the Dmem=20 >>> section's size is not divisible by 256. But tbh, I find it odd that=20 >>> `dma_wr` doesn't check that FalconDmaLoadTarget's length is a >>> multiple of 256 anyway, because it looks like it'll write a bunch of >>> unrelated bytes (since it rounds up to the nearest 256 to copy). >>> >>> Maybe we should enforce that `FalconDmaLoadTarget` length is divisible >>> by 256? >>> >>> For this series if for all firmwares it's divisible by 256 then I think >>> it's fine to leave this as is for now, but I do find the lack of >>> checking in `dma_wr` (or anywhere else for FalconDmaLoadTarget) a bit >>> odd. >> >> All coherent allocations are page-aligned (and use full pages), so we >> are safe in terms of overflows. > > Let's not rely on this behaviour. There is no guarantee on what's at the = end > of allocation whatsoever. There's no guarantee that it will be initialize= d. > Even with __GFP_ZERO only the size provided will be zeroed. > > If the GPU is going to read beyond ranges covered by `Coherent` (not just= rely > on the alignment), let's align up the allocation. > >> >> Also `dma_wr` uses `div_ceil(256)` which will skip the last data block >> entirely if it is not a multiple of 256. It might be a bit more robust >> to explicitly check that the size is a multiple of 256 and return an >> error if that is not the case indeed. > > div_ceil will not skip the last block, it will over-read beyond the end. > div_floor would have skipped the block. Ooopsie yes, of course. Making `dma_wr` check that the data is a multiple of 256 is the simplest, I'll send a patch for that (with maybe some padding code as I think I remember Turing at least did not always follow the 256-alignment requirement).