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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b7b1a5fbesm301940766b.37.2026.03.30.07.55.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Mar 2026 07:55:40 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 30 Mar 2026 16:55:40 +0200 Message-Id: Subject: Re: [PATCH 2/5] dt-bindings: clock: qcom,milos-camcc: Document interconnect path From: "Luca Weiss" To: "Mike Tipton" , "Konrad Dybcio" Cc: "Krzysztof Kozlowski" , "Luca Weiss" , "Taniya Das" , "Georgi Djakov" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260116-milos-camcc-icc-v1-0-400b7fcd156a@fairphone.com> <20260116-milos-camcc-icc-v1-2-400b7fcd156a@fairphone.com> <20260117-efficient-fractal-sloth-aaf7c2@quoll> <59d9f7ff-4111-4304-a76c-40f4000545f5@oss.qualcomm.com> <9f8619d4-43ac-4bc0-9598-c498d59a27b8@oss.qualcomm.com> In-Reply-To: Hi Mike, On Tue Mar 24, 2026 at 3:48 AM CET, Mike Tipton wrote: > On Mon, Jan 19, 2026 at 11:28:07AM +0100, Konrad Dybcio wrote: >>=20 >>=20 >> On 1/19/26 11:20 AM, Konrad Dybcio wrote: >> > On 1/17/26 12:46 PM, Krzysztof Kozlowski wrote: >> >> On Fri, Jan 16, 2026 at 02:17:21PM +0100, Luca Weiss wrote: >> >>> Document an interconnect path for camcc that's required to enable >> >>> the CAMSS_TOP_GDSC power domain. >> >> >> >> I find it confusing. Enabling GDSC power domains is done via power >> >> domains, not via interconnects. Do not represent power domains as >> >> interconnects, it's something completely different. >> >=20 >> > The name of the power domains is CAMSS_TOP_GDSC (seems you misread) >> >=20 >> > For the power domain to successfully turn on, the MNoC needs to be >> > turned on (empirical evidence). The way to do it is to request a >> > nonzero vote on this interconnect path >> >=20 >> > (presumably because the GDSC or its invisible providers require >> > something connected over that bus to carry out their enable sequences)= . > > The GDSC itself shouldn't depend on MMNOC in order to turn on properly. > It should turn on just fine without it. There *is* a dependency between > CAM_TOP_GDSC and MMNOC, but it's in the opposite direction. I can personally just write from practical experience, as Qualcomm doesn't share any relevant documentation with OEMs. Without this patch the GDSC refuses to turn on. [ 291.055839] ------------[ cut here ]------------ [ 291.055860] cam_cc_camss_top_gdsc status stuck at 'off' [ 291.055878] WARNING: drivers/clk/qcom/gdsc.c:178 at gdsc_toggle_logic+0x= 138/0x144, CPU#4: hexdump/1995 With the patch it turns on just fine, no issues seen. As Konrad has written, originally I didn't see any issue because that interconnect was being kept alive by simple-framebuffer where I've added 'interconnects' to keep the framebuffer alive. However when testing without this, the GDSC would refuse to turn on, which led me to this patch series. Additionally you can see in downstream devicetree you can also see an interconnect defined for the "cam_cc_camss_top_gdsc" node: https://gerrit-public.fairphone.software/plugins/gitiles/platform/vendor/qc= om/proprietary/devicetree/+/refs/heads/odm/rc/target/15/fp6/fps_overlay/vol= cano.dtsi#2943 Regards Luca