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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9d6e7f1a3bsm283831866b.62.2026.04.13.01.55.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Apr 2026 01:55:36 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 13 Apr 2026 10:55:35 +0200 Message-Id: Cc: "Bjorn Andersson" , "Linus Walleij" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller From: "Luca Weiss" To: "Konrad Dybcio" , "Luca Weiss" , "Dmitry Baryshkov" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> <20260128-sm6350-lpi-tlmm-v1-4-36583f2a2a2a@fairphone.com> <91812db8-9774-468e-8a8b-10699a63310c@oss.qualcomm.com> In-Reply-To: <91812db8-9774-468e-8a8b-10699a63310c@oss.qualcomm.com> Hi Konrad, On Thu Jan 29, 2026 at 12:19 PM CET, Konrad Dybcio wrote: > On 1/29/26 9:32 AM, Luca Weiss wrote: >> On Wed Jan 28, 2026 at 11:16 PM CET, Dmitry Baryshkov wrote: >>> On Wed, Jan 28, 2026 at 01:26:52PM +0100, Luca Weiss wrote: >>>> Add LPASS LPI pinctrl node required for audio functionality on SM6350. >>>> >>>> Signed-off-by: Luca Weiss >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 +++++++++++++++++++++++++++= +++++++++ >>>> 1 file changed, 66 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dt= s/qcom/sm6350.dtsi >>>> index 9f9b9f9af0da..b1fb6c812da7 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>> @@ -1448,6 +1448,72 @@ compute-cb@5 { >>>> }; >>>> }; >>>> =20 >>>> + lpass_tlmm: pinctrl@33c0000 { >>>> + compatible =3D "qcom,sm6350-lpass-lpi-pinctrl"; >>>> + reg =3D <0x0 0x033c0000 0x0 0x20000>, >>>> + <0x0 0x03550000 0x0 0x10000>; >>>> + gpio-controller; >>>> + #gpio-cells =3D <2>; >>>> + gpio-ranges =3D <&lpass_tlmm 0 0 15>; >>>> + >>>> + clocks =3D <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPL= E_NO>, >>>> + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >>>> + clock-names =3D "core", >>>> + "audio"; >>>> + >>>> + i2s1_active: i2s1-active-state { >>>> + clk-pins { >>>> + pins =3D "gpio6"; >>>> + function =3D "i2s1_clk"; >>>> + drive-strength =3D <8>; >>>> + bias-disable; >>>> + output-high; >>> >>> This looks suspicious for the clock pin. >>> >>>> + }; >>>> + >>>> + ws-pins { >>>> + pins =3D "gpio7"; >>>> + function =3D "i2s1_ws"; >>>> + drive-strength =3D <8>; >>>> + bias-disable; >>>> + output-high; >>> >>> The same >>> >>>> + }; >>>> + >>>> + data-pins { >>>> + pins =3D "gpio8", "gpio9"; >>>> + function =3D "i2s1_data"; >>>> + drive-strength =3D <8>; >>>> + bias-disable; >>>> + output-high; >>> >>> And here. >>=20 >> I've taken this pinctrl from downstream lagoon-lpi.dtsi. There the >> active config for these pins have "output-high;" set. >>=20 >> And fwiw this pinctrl works fine at runtime for driving the speaker. > > I tried to find an answer. > > A doc for this SoC says that i2s clock pins should be at output-low > (2 mA) when muxed to the i2s_xxx function, with no information about > bias settings (perhaps bias-disable), and in sleep they should be the > same (minus the drive strength note, but 2mA is the lowest setting) > > I am further confused because the output-enable bit in the cfg > register specifically says "when in GPIO mode" Thanks for checking. What should we do here now? Follow what you found in the docs, or follow what downstream is doing (8ma output-high)? https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/d= evicetree/+/refs/heads/int/15/fp4/qcom/lagoon-lpi.dtsi#219 I think apart from this question, this patchset should be ready to land. Regards Luca p.s. I also briefly checked Google's repositories (which is the only known place to have a commit history with devicetree since the devicetree was just shipped with vendor/qcom/proprietary for everybody else, without history) but there there's also no hint whether there's any specific reason they deviate. https://android.googlesource.com/kernel/msm-extra/devicetree/+log/refs/tags= /android-11.0.0_r0.56/qcom/lagoon-lpi.dtsi