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charset=UTF-8 Date: Tue, 19 May 2026 10:32:16 +0900 Message-Id: Cc: "John Hubbard" , "Alistair Popple" , "Timur Tabi" , "Eliot Courtney" , , , , Subject: Re: [PATCH v5 6/7] gpu: nova-core: gsp: move chipset-specific parts of the boot process into a HAL From: "Eliot Courtney" To: "Alexandre Courbot" , "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260515-nova-unload-v5-0-c4d6250ad160@nvidia.com> <20260515-nova-unload-v5-6-c4d6250ad160@nvidia.com> In-Reply-To: <20260515-nova-unload-v5-6-c4d6250ad160@nvidia.com> X-ClientProxiedBy: TY4P301CA0080.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:36f::8) To SN1PR12MB2368.namprd12.prod.outlook.com (2603:10b6:802:32::23) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2353:EE_|DS7PR12MB5717:EE_ X-MS-Office365-Filtering-Correlation-Id: c0b04208-08f1-499a-23b8-08deb54677e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|10070799003|366016|11063799003|4143699003|18002099003|56012099003|22082099003; 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Move > the parts that are chipset-specific under a HAL. > > This does not change much at the moment, since the differences between > Turing and Ampere are rather benign, but will become critical to > properly support the FSP boot process used by Hopper and Blackwell. > > The Hopper/Blackwell support is not merged yet, so their HAL is a stub > for now. > > This patch is intended to be a mechanical code extraction with no > behavioral changes. > > Signed-off-by: Alexandre Courbot > --- > +/// Load and run the booter firmware. > +fn run_booter( > + dev: &device::Device, > + bar: &Bar0, > + chipset: Chipset, > + sec2_falcon: &Falcon, > + wpr_meta: &Coherent, > +) -> Result { > + BooterFirmware::new( > + dev, > + BooterKind::Loader, > + chipset, > + FIRMWARE_VERSION, > + sec2_falcon, > + bar, > + )? > + .run(dev, bar, sec2_falcon, wpr_meta) > +} nit: This method mostly just forwards arguments, it feels a bit odd to split this, but not e.g. GspSequencer::run() below. IMO you can just do this inline. I see you are just moving code though, so no worries. > + > +struct Tu102; > + > +impl GspHal for Tu102 { > + fn boot( > + &self, > + gsp: Pin<&mut Gsp>, > + dev: &device::Device, > + bar: &Bar0, > + chipset: Chipset, > + fb_layout: &FbLayout, > + wpr_meta: &Coherent, > + gsp_falcon: &Falcon, > + sec2_falcon: &Falcon, > + ) -> Result { > + let bios =3D Vbios::new(dev, bar)?; > + > + // FWSEC-FRTS is not executed on chips where the FRTS region siz= e is 0 (e.g. GA100). > + if !fb_layout.frts.is_empty() { > + run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, fb_layo= ut)?; > + } > + > + gsp_falcon.reset(bar)?; > + let libos_handle =3D gsp.libos.dma_handle(); > + let (mbox0, mbox1) =3D gsp_falcon.boot( > + bar, > + Some(libos_handle as u32), > + Some((libos_handle >> 32) as u32), > + )?; > + dev_dbg!(dev, "GSP MBOX0: {:#x}, MBOX1: {:#x}\n", mbox0, mbox1); > + > + dev_dbg!( > + dev, > + "Using SEC2 to load and run the booter_load firmware...\n" > + ); > + > + run_booter(dev, bar, chipset, sec2_falcon, wpr_meta)?; > + > + Ok(()) > + } > + > + fn post_boot( > + &self, > + gsp: Pin<&mut Gsp>, > + dev: &device::Device, > + bar: &Bar0, > + gsp_fw: &GspFirmware, > + gsp_falcon: &Falcon, > + sec2_falcon: &Falcon, > + ) -> Result { > + // Create and run the GSP sequencer. > + let seq_params =3D GspSequencerParams { > + bootloader_app_version: gsp_fw.bootloader.app_version, > + libos_dma_handle: gsp.libos.dma_handle(), > + gsp_falcon, > + sec2_falcon, > + dev: dev.into(), > + bar, > + }; > + GspSequencer::run(&gsp.cmdq, seq_params)?; > + > + Ok(()) > + } > +} > + > +const TU102: Tu102 =3D Tu102; > +pub(super) const TU102_HAL: &dyn GspHal =3D &TU102; Reviewed-by: Eliot Courtney