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charset=UTF-8 Date: Tue, 02 Jun 2026 16:56:02 +0900 Message-Id: Cc: "Timur Tabi" , "Alistair Popple" , "Eliot Courtney" , "Shashank Sharma" , "Zhi Wang" , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , "LKML" Subject: Re: [PATCH v12 12/22] gpu: nova-core: Hopper/Blackwell: add FSP secure boot completion waiting From: "Eliot Courtney" To: "John Hubbard" , "Danilo Krummrich" , "Alexandre Courbot" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260602032111.224790-1-jhubbard@nvidia.com> <20260602032111.224790-13-jhubbard@nvidia.com> In-Reply-To: <20260602032111.224790-13-jhubbard@nvidia.com> X-ClientProxiedBy: TY4P286CA0135.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:37f::18) To BL0PR12MB2353.namprd12.prod.outlook.com (2603:10b6:207:4c::31) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2353:EE_|MW6PR12MB8662:EE_ X-MS-Office365-Filtering-Correlation-Id: 9c65864e-372e-4c5c-fbb5-08dec07c66c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|10070799003|7416014|376014|1800799024|22082099003|18002099003|11063799006|4143699003|56012099006; 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The > driver must wait for FSP secure boot to complete before continuing > with GSP bring-up. Poll for boot success with a 5-second timeout, and > return the FSP interface only on success so that later Chain of Trust > operations cannot run before FSP is ready. The interface owns the FSP > falcon and the FMC firmware. > > Co-developed-by: Alexandre Courbot > Signed-off-by: Alexandre Courbot > Signed-off-by: John Hubbard > --- > drivers/gpu/nova-core/falcon/fsp.rs | 1 - > drivers/gpu/nova-core/fsp.rs | 73 ++++++++++++++++++++++++++ > drivers/gpu/nova-core/fsp/hal.rs | 27 ++++++++++ > drivers/gpu/nova-core/fsp/hal/gb202.rs | 23 ++++++++ > drivers/gpu/nova-core/fsp/hal/gh100.rs | 23 ++++++++ > drivers/gpu/nova-core/gsp/hal/gh100.rs | 6 ++- > drivers/gpu/nova-core/nova_core.rs | 1 + > drivers/gpu/nova-core/regs.rs | 36 +++++++++++++ > 8 files changed, 187 insertions(+), 3 deletions(-) > create mode 100644 drivers/gpu/nova-core/fsp.rs > create mode 100644 drivers/gpu/nova-core/fsp/hal.rs > create mode 100644 drivers/gpu/nova-core/fsp/hal/gb202.rs > create mode 100644 drivers/gpu/nova-core/fsp/hal/gh100.rs > > diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/= falcon/fsp.rs > index c4a9ce8a47f8..d9f87262e8b1 100644 > --- a/drivers/gpu/nova-core/falcon/fsp.rs > +++ b/drivers/gpu/nova-core/falcon/fsp.rs > @@ -15,7 +15,6 @@ > }; > =20 > /// Type specifying the `Fsp` falcon engine. Cannot be instantiated. > -#[expect(dead_code)] > pub(crate) struct Fsp(()); > =20 > impl RegisterBase for Fsp { > diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs > new file mode 100644 > index 000000000000..f3524137d9f7 > --- /dev/null > +++ b/drivers/gpu/nova-core/fsp.rs > @@ -0,0 +1,73 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFIL= IATES. All rights reserved. > + > +//! FSP (Foundation Security Processor) interface for Hopper/Blackwell G= PUs. > +//! > +//! Hopper/Blackwell use a simplified firmware boot sequence: FMC, then = FSP, then GSP. > +//! Unlike Turing/Ampere/Ada, there is no SEC2 (Security Engine 2) usage= . > +//! FSP handles secure boot directly using FMC firmware and Chain of Tru= st. > + > +use kernel::{ > + device, > + io::poll::read_poll_timeout, > + prelude::*, > + time::Delta, // > +}; > + > +use crate::{ > + driver::Bar0, > + falcon::{ > + fsp::Fsp as FspEngine, > + Falcon, // > + }, > + firmware::fsp::FspFirmware, > + gpu::Chipset, > + regs, // > +}; > + > +mod hal; > + > +/// FSP interface for Hopper/Blackwell GPUs. > +/// > +/// An `Fsp` is produced by [`Fsp::wait_secure_boot`], which only return= s once FSP secure boot > +/// has completed. It owns the FSP falcon and the FMC firmware, which ar= e used for the subsequent > +/// Chain of Trust boot. > +pub(crate) struct Fsp { > + #[expect(dead_code)] > + falcon: Falcon, > + #[expect(dead_code)] > + fsp_fw: FspFirmware, > +} > + > +impl Fsp { > + /// Waits for FSP secure boot completion, then returns the [`Fsp`] i= nterface. > + /// > + /// Polls the thermal scratch register until FSP signals boot comple= tion or the timeout > + /// elapses. Returning an [`Fsp`] only on success guarantees, at the= API level, that the > + /// interface is not used before secure boot has completed. > + pub(crate) fn wait_secure_boot( > + dev: &device::Device, > + bar: &Bar0, > + chipset: Chipset, > + fsp_fw: FspFirmware, What about constructing FspFirmware inside `wait_secure_boot`? It fits the concept of having this Fsp object own and control the FSP. This also matches the pattern of Gsp::boot creating its own GspFirmware. > + ) -> Result { > + /// FSP secure boot completion timeout in milliseconds. > + const FSP_SECURE_BOOT_TIMEOUT_MS: i64 =3D 5000; > + > + let hal =3D hal::fsp_hal(chipset).ok_or(ENOTSUPP)?; > + let falcon =3D Falcon::::new(dev, chipset)?; > + > + read_poll_timeout( > + || Ok(hal.fsp_boot_status(bar)), > + |&status| status =3D=3D regs::NV_THERM_I2CS_SCRATCH_FSP_BOOT= _COMPLETE_STATUS_SUCCESS, > + Delta::from_millis(10), > + Delta::from_millis(FSP_SECURE_BOOT_TIMEOUT_MS), > + ) > + .map_err(|_| { > + dev_err!(dev, "FSP secure boot completion timeout\n"); > + ETIMEDOUT > + })?; nit: this can just be inspect_err(), it will be ETIMEDOUT if it times out. > + > + Ok(Fsp { falcon, fsp_fw }) > + } > +} > diff --git a/drivers/gpu/nova-core/fsp/hal.rs b/drivers/gpu/nova-core/fsp= /hal.rs > new file mode 100644 > index 000000000000..83d1e7daa998 > --- /dev/null > +++ b/drivers/gpu/nova-core/fsp/hal.rs > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFIL= IATES. All rights reserved. > + > +use crate::{ > + driver::Bar0, > + gpu::{ > + Architecture, > + Chipset, // > + }, > +}; > + > +mod gb202; > +mod gh100; > + > +pub(super) trait FspHal { > + /// Returns the secure boot status from the architecture-specific `N= V_THERM_I2CS_SCRATCH` register. > + fn fsp_boot_status(&self, bar: &Bar0) -> u32; > +} > + > +/// Returns the FSP HAL, or `None` if the architecture doesn't support F= SP. > +pub(crate) fn fsp_hal(chipset: Chipset) -> Option<&'static dyn FspHal> { nit: this can be pub(super) With above changes, Reviewed-by: Eliot Courtney