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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-bf05176fd20sm838285766b.7.2026.06.08.00.22.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 Jun 2026 00:22:29 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 08 Jun 2026 09:22:28 +0200 Message-Id: Cc: "Ajit Pandey" , "Imran Shaik" , "Jagadeesh Kona" , , , , , , Subject: Re: [PATCH 4/5] arm64: dts: qcom: Add gp_mn pin state for GP M/N clock output From: "Luca Weiss" To: "Taniya Das" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Linus Walleij" , "Richard Cochran" , "Konrad Dybcio" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260602-pdm_clk_gp_mnd_v1-v1-0-1522662b6c53@oss.qualcomm.com> <20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com> In-Reply-To: <20260602-pdm_clk_gp_mnd_v1-v1-4-1522662b6c53@oss.qualcomm.com> On Tue Jun 2, 2026 at 5:21 PM CEST, Taniya Das wrote: > Add pinctrl states for the GP M/N divider clock output pin across > multiple Qualcomm SoCs: > > wire it to the GP M/N clock controller node via pinctrl-0. > - kodiak (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). kodiak (sc7280) - this should be gpio60? > - lemans (sa8775p): Add gp_mn_active state on gpio35 (gp_mn function). > - monaco (qcs8300): Add gp_mn_active state on gpio32 (gp_mn function). > > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/kodiak.dtsi | 7 +++++++ > arch/arm64/boot/dts/qcom/lemans.dtsi | 7 +++++++ > arch/arm64/boot/dts/qcom/monaco.dtsi | 7 +++++++ > 3 files changed, 21 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/q= com/kodiak.dtsi > index fa540d8c2615dc02d941eb16bc7253204c2750bd..1ff9e1598d00429c03b2bcae4= 1fa370ab2c892bd 100644 > --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi > +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi > @@ -5908,6 +5908,13 @@ edp_hot_plug_det: edp-hot-plug-det-state { > function =3D "edp_hot"; > }; > =20 > + gp_mn_active: gp_mn_active-state { > + pins =3D "gpio35"; gpio60? I still find it incredible that the QCM6490 datasheet (80-20659-1 Rev. AJ) doesn't even mention this functionality on GPIO_60.. I wonder what else is hidden on these SoCs. Regards Luca > + function =3D "gp_mn"; > + drive-strength =3D <2>; > + bias-disable; > + }; > + > mi2s0_data0: mi2s0-data0-state { > pins =3D "gpio98"; > function =3D "mi2s0_data0"; > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/q= com/lemans.dtsi > index 353a6e6fd3acb22ef228bee340212b8b2c300957..19f8cf4e15482947f60491880= 50c370340afaead 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -6022,6 +6022,13 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { > bias-disable; > }; > =20 > + gp_mn_active: gp_mn_active-state { > + pins =3D "gpio35"; > + function =3D "gp_mn"; > + drive-strength =3D <2>; > + bias-disable; > + }; > + > hs0_mi2s_active: hs0-mi2s-active-state { > pins =3D "gpio114", "gpio115", "gpio116", "gpio117"; > function =3D "hs0_mi2s"; > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/q= com/monaco.dtsi > index e4c8466f941bdba04f99b988fd7bf5afd926b31d..ebe5889daa5300efa7857314e= 9170d7d2fc33ef7 100644 > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > @@ -6433,6 +6433,13 @@ dp_hot_plug_det: dp-hot-plug-det-state { > bias-disable; > }; > =20 > + gp_mn_active: gp_mn_active-state { > + pins =3D "gpio32"; > + function =3D "gp_mn"; > + drive-strength =3D <2>; > + bias-disable; > + }; > + > hs0_mi2s_active: hs0-mi2s-active-state { > pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; > function =3D "hs0_mi2s";