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[2001:1c00:3b89:c600:b4d0:bc9f:f60e:913a]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6937948fc99sm682580a12.23.2026.06.12.06.46.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Jun 2026 06:46:22 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 12 Jun 2026 15:46:21 +0200 Message-Id: Subject: Re: [PATCH 1/2] arm64: dts: qcom: kodiak: Sort pinctrl subnodes by pins From: "Luca Weiss" To: "Vladimir Zapolskiy" , "Bjorn Andersson" , "Konrad Dybcio" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260612-kodiak-cam-mclk-v1-0-fd294ff003a2@fairphone.com> In-Reply-To: On Fri Jun 12, 2026 at 2:59 PM CEST, Vladimir Zapolskiy wrote: > As documented in the "Devicetree Sources (DTS) Coding Style" document, > pinctrl subnodes should be sorted by the pins property. Do this once for > kodiak.dtsi so that future additions can be added at the right places. > > No functional change intended, verified with dtx_diff. > > Signed-off-by: Luca Weiss > --- > arch/arm64/boot/dts/qcom/kodiak.dtsi | 1382 +++++++++++++++++----------= ------- > 1 file changed, 691 insertions(+), 691 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/q= com/kodiak.dtsi > index fa540d8c2615..62daef726d32 100644 > --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi > +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi > + qup_uart12_cts: qup-uart12-cts-state { > + pins =3D "gpio48"; > + function =3D "qup14"; > + }; > + > + qup_uart12_rts: qup-uart12-rts-state { > + pins =3D "gpio49"; > + function =3D "qup14"; > + }; > + > + qup_uart12_tx: qup-uart12-tx-state { > + pins =3D "gpio50"; > + function =3D "qup14"; > + }; > > I understand and support the intention to keep this change non-functional= , > but this pad "gpio50" is for qup16 also, right? According to my QCM6490 data sheet, GPIO_50 has these functions: * UART for qup14 (OK) * SPI for qup14 (OK) * SPI for qup16 (no pinctrl) > > Similarly pads "gpio54"/"gpio55" for qup14 function, "gpio62"/"gpio63" > for qup16 function, I find all of these are missing on the original list. GPIO_54: * UART qup15 (OK) * SPI qup15 (OK) * SPI qup14 (no pinctrl) GPIO_55: * UART qup15 (OK) * SPI qup15 (OK) * SPI qup14 (no pinctrl) GPIO_62: * UART qup17 (OK) * SPI qup17 (OK) * SPI qup16 (no pinctrl) GPIO_63: * UART qup16 (?) * SPI qup16 (lane 3) (?) * SPI qup16 (lane 5) (?) But the GPIO_63 looks weird, is the data sheet wrong?! Where would UART_RX of QUP1 SE7 go? Maybe it should be UART qup17 and SPI qup17 and then SPI qup16 ?? Can somebody at Qualcomm please check 80-20659-1 Rev. AM and maybe make the apppriate people there aware? So yes Vladimir, you're correct. Some pinctrl definitions for those SPI QUPs are not defined. And the datasheet seems wrong as well. > Reviewed-by: Vladimir Zapolskiy Thanks for checking! Regards Luca