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[144.178.202.142]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d3859f69sm407039066b.27.2026.07.10.06.58.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jul 2026 06:58:36 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 10 Jul 2026 15:58:35 +0200 Message-Id: Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 2/4] arm64: dts: qcom: milos: add OSM L3 node From: "Luca Weiss" To: "Konrad Dybcio" , "Luca Weiss" , "Georgi Djakov" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Sibi Sankar" , "Bjorn Andersson" , "Konrad Dybcio" , "Alexander Koskovich" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> <20260710-milos-cpu-opp-v1-2-ae7f4b09bc77@fairphone.com> In-Reply-To: Hi Konrad, On Fri Jul 10, 2026 at 3:44 PM CEST, Konrad Dybcio wrote: > On 7/10/26 11:22 AM, Luca Weiss wrote: >> Add the OSC L3 Cache controller node. >>=20 >> Signed-off-by: Luca Weiss >> --- > > I'd suggest to squash this series into 1 big patch, without patch > 3 applied the OSM driver will engage and perform sync_state (with > 0 requests, so it will vote for 0/lowest) and the system > performance will be tragic Fair point I think, I took the structure of the patches from sm8650 which had it split this way but yes, it doesn't make too much sense in terms of keeping system performance alive through bisection. Will do so in v2. Regards Luca > > Konrad