mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: "Gary Guo" <gary@garyguo.net>
To: "Alexandre Courbot" <acourbot@nvidia.com>, "Gary Guo" <gary@garyguo.net>
Cc: "Danilo Krummrich" <dakr@kernel.org>,
	"Alice Ryhl" <aliceryhl@google.com>,
	"Daniel Almeida" <daniel.almeida@collabora.com>,
	"Miguel Ojeda" <ojeda@kernel.org>,
	"Boqun Feng" <boqun@kernel.org>,
	"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
	"Benno Lossin" <lossin@kernel.org>,
	"Andreas Hindborg" <a.hindborg@kernel.org>,
	"Trevor Gross" <tmgross@umich.edu>,
	"Tamir Duberstein" <tamird@kernel.org>,
	"Onur Özkan" <work@onurozkan.dev>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	driver-core@lists.linux.dev, rust-for-linux@vger.kernel.org,
	linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev,
	dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH 01/10] rust: io: register: allow explicit base type specification
Date: Fri, 24 Jul 2026 14:22:39 +0100	[thread overview]
Message-ID: <DK6U0LR7D57N.3FW1CZG9R42YF@garyguo.net> (raw)
In-Reply-To: <DK6LF1ODPWC3.3QQV3SXQ55SXP@nvidia.com>

On Fri Jul 24, 2026 at 7:38 AM BST, Alexandre Courbot wrote:
> nit: the base-commit trailer points to a commit that only exists in
> linux-next (next-20260720) and is not easily discoverable - it would
> help if you could mention the base in human-resolvable form in the cover
> letter.
>
> On Wed Jul 22, 2026 at 1:54 AM JST, Gary Guo wrote:
>> Currently registers work for all untyped I/O regions, which is not ideal.
>> It allows registers defined for device A to work for another device B and
>> there is no safeguarding at all.
>
> This doesn't sound like a real concern. Registers are typically local to
> a driver, so one cannot use registers for device A on device B even now.
> And within the same crate registers can be isolated by module if needed.

Even for a single driver you don't want to mix register definitions. E.g. if
you have more bars, e.g. if you have subregions of registers, like PFALCON and
PFALCON2.

Your relative register design uses an artifical marker type to distinguish
between two different subregions, which is a very good motiviation to say that
registers should be typed.

>
> Even if we restrict the base type, the examples given in this patch only
> partially address the issue: registers from different drivers using
> regions of identical sizes could be used interchangeably without
> complaint.

This patch set gives you the way to do newtype on regions. Ideally all drivers
would eventually use that and not use the `Region` type.

>
> So I don't think this patchset addresses this particular problem, for
> which namespace isolation is the correct solution anyway.
>
>>
>> All users of the `register!` macro know what type it will be operating on,
>> and that type is consistent across the driver. Therefore, add a `base`
>> parameter to `register!`.
>>
>> Currently this parameter is unused in the generated code; it will be used
>> when all users of `register!` is converted to gain the parameter.
>>
>> Signed-off-by: Gary Guo <gary@garyguo.net>
>> ---
>>  rust/kernel/io.rs          |  4 +++
>>  rust/kernel/io/register.rs | 79 ++++++++++++++++++++++++++++++++++++++++++----
>>  2 files changed, 76 insertions(+), 7 deletions(-)
>>
>> diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs
>> index 95f46bb75f9e..c5f07c38e59e 100644
>> --- a/rust/kernel/io.rs
>> +++ b/rust/kernel/io.rs
>> @@ -883,6 +883,8 @@ fn try_write<T, L>(self, location: L, value: T) -> Result
>>      /// };
>>      ///
>>      /// register! {
>> +    ///     base: Region;
>> +    ///
>>      ///     VERSION(u32) @ 0x100 {
>>      ///         15:8 major;
>>      ///         7:0  minor;
>> @@ -1028,6 +1030,8 @@ fn write<T, L>(self, location: L, value: T)
>>      /// };
>>      ///
>>      /// register! {
>> +    ///     base: Region<0x1000>;
>
> I'd prefer if we could limit the `base:` parameter to registers defined
> against a specific block (like the current relative registers). Having
> it on all register definitions adds an artificial limitation (that e.g.
> regions must be of a given size, which may not suit drivers that support
> several generations of hardware with varying BAR sizes).

This is more or less intended. Your driver code would have a fixed known minimum
size, even if your code works with multiple generation of hardware.

It's just that code touches registers outside the known minimum size would need
to use fallible accessors because the bar is not guaranteed to be large enough.

If the code is written so you have dedicated HAL paths that the register will
always exist, your should just create a new type for the larger region of
specific hardware generation and define the register on that instead.

E.g.
    
    #[repr(align(4))]
    #[derive(FromBytes, IntoBytes)]
    struct MyNewGenHardware([u8; SZ_1G]); // This new hardware gen has huge register space!

    register! {
        base: MyNewGenHardware;
    }

>
> Top-level registers are currently working fine without this, so it
> doesn't seem justified except by the safeguarding argument, which I
> don't think is relevant here.

This *could* be done, but this means that we need to change register traits to
not have `Base` assoc type but have it as generics. It is however problematic
from trait coherence POV, because Rust complains that downstream crate can
implement

    impl FixedRegister<MyRegion> for () {}

and conflict with blanket impl.

Also I think this is not really needed with strongly typed regions (see above),
hence the design.

Best,
Gary

>
> The syntax (specifying `base:` only once at the top of a register block)
> is a great improvement over the current one; if I were to pursue my own
> fixup series I would definitely have adopted it.
>
> Still going through the series in detail but wanted to raise this point
> first. Overall I think I like the direction, it makes the falcon
> register accesses read much more naturally.



  reply	other threads:[~2026-07-24 13:22 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-21 16:54 [PATCH 00/10] rust: io: make register bases typed and remove relative registers Gary Guo
2026-07-21 16:54 ` [PATCH 01/10] rust: io: register: allow explicit base type specification Gary Guo
2026-07-24  6:38   ` Alexandre Courbot
2026-07-24 13:22     ` Gary Guo [this message]
2026-07-27  5:27       ` Eliot Courtney
2026-07-27  8:14         ` Alexandre Courbot
2026-07-28 19:12           ` John Hubbard
2026-07-30 14:50             ` Alexandre Courbot
2026-07-21 16:54 ` [PATCH 02/10] gpu: nova-core: specify base type for registers Gary Guo
2026-07-28  6:47   ` Alexandre Courbot
2026-07-21 16:54 ` [PATCH 03/10] drm/tyr: " Gary Guo
2026-07-21 16:54 ` [PATCH 04/10] samples: rust: pci: " Gary Guo
2026-07-21 16:54 ` [PATCH 05/10] rust: io: register: make register have a typed base Gary Guo
2026-07-21 16:54 ` [PATCH 06/10] rust: io: add static `cast()` method for views Gary Guo
2026-07-21 16:54 ` [PATCH 07/10] rust: io: add subregion method with compile-time check Gary Guo
2026-07-28  7:21   ` Alexandre Courbot
2026-07-21 16:54 ` [PATCH 08/10] gpu: nova-core: use projection for PFALCON and PFALCON2 registers Gary Guo
2026-07-28  6:45   ` Alexandre Courbot
2026-07-28 10:24     ` Gary Guo
2026-07-28 15:09       ` Alexandre Courbot
2026-07-28 17:01         ` Danilo Krummrich
2026-07-28 18:26           ` Gary Guo
2026-07-28 18:56             ` Danilo Krummrich
2026-07-28 19:03               ` Gary Guo
2026-07-28 19:30                 ` Miguel Ojeda
2026-07-28 20:07                 ` Danilo Krummrich
2026-07-29 10:24                   ` Gary Guo
2026-07-29 19:28                     ` Danilo Krummrich
2026-07-29 19:51                       ` Gary Guo
2026-07-21 16:54 ` [PATCH 09/10] gpu: nova-core: convert hshub0 from relative register to projection Gary Guo
2026-07-21 16:54 ` [PATCH 10/10] rust: io: register: remove relative registers Gary Guo

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DK6U0LR7D57N.3FW1CZG9R42YF@garyguo.net \
    --to=gary@garyguo.net \
    --cc=a.hindborg@kernel.org \
    --cc=acourbot@nvidia.com \
    --cc=airlied@gmail.com \
    --cc=aliceryhl@google.com \
    --cc=bhelgaas@google.com \
    --cc=bjorn3_gh@protonmail.com \
    --cc=boqun@kernel.org \
    --cc=dakr@kernel.org \
    --cc=daniel.almeida@collabora.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=driver-core@lists.linux.dev \
    --cc=kwilczynski@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lossin@kernel.org \
    --cc=nova-gpu@lists.linux.dev \
    --cc=ojeda@kernel.org \
    --cc=rust-for-linux@vger.kernel.org \
    --cc=simona@ffwll.ch \
    --cc=tamird@kernel.org \
    --cc=tmgross@umich.edu \
    --cc=work@onurozkan.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®