From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Antonin Malzieu Ridolfi via B4 Relay"
<devnull+dev.nanonej.com@kernel.org>
Cc: <dev@nanonej.com>, "Danilo Krummrich" <dakr@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>, <nova-gpu@lists.linux.dev>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
<daniel.almeida@collabora.com>
Subject: Re: [PATCH 2/3] gpu: nova-core: Move PFB registers definitions
Date: Sat, 25 Jul 2026 22:27:19 +0900 [thread overview]
Message-ID: <DK7OQQAYBCQV.3PKBRU8CYCUNG@nvidia.com> (raw)
In-Reply-To: <20260721-nova-core-regs-split-v1-2-384fa2a42244@nanonej.com>
On Wed Jul 22, 2026 at 12:41 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote:
> From: Antonin Malzieu Ridolfi <dev@nanonej.com>
>
Every patch needs a commit message, even if short.
(also please check whether the issue raised by Sashiko [1] has merit)
[1] https://sashiko.dev/#/patchset/20260721-nova-core-regs-split-v1-0-384fa2a42244@nanonej.com?part=2
One more comment inline, but this is pretty much what I had in mind; so
looking pretty good imho!
> Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
> Suggested-by: Danilo Krummrich <dakr@kernel.org>
> Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
> ---
> drivers/gpu/nova-core/fb.rs | 4 +-
> drivers/gpu/nova-core/fb/hal/ga100.rs | 8 ++-
> drivers/gpu/nova-core/fb/hal/gb100.rs | 6 +-
> drivers/gpu/nova-core/fb/hal/gb202.rs | 6 +-
> drivers/gpu/nova-core/fb/hal/gh100.rs | 6 +-
> drivers/gpu/nova-core/fb/hal/tu102.rs | 8 ++-
> drivers/gpu/nova-core/fb/regs.rs | 132 +++++++++++++++++++++++++++++++++-
> drivers/gpu/nova-core/regs.rs | 127 --------------------------------
> 8 files changed, 155 insertions(+), 142 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs
> index 864a34ca20b8..59e715b73479 100644
> --- a/drivers/gpu/nova-core/fb.rs
> +++ b/drivers/gpu/nova-core/fb.rs
> @@ -275,8 +275,8 @@ pub(crate) fn new(chipset: Chipset, bar: Bar0<'_>, gsp_fw: &GspFirmware) -> Resu
> /// Returns `None` if the WPR2 region is not set.
> pub(crate) fn wpr2_range(bar: Bar0<'_>) -> Option<Range<u64>> {
> let (wpr2_lo, wpr2_hi) = (
> - bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO),
> - bar.read(crate::regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI),
> + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO),
> + bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI),
> );
>
> if !wpr2_hi.is_wpr2_set() {
> diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs
> index 3cc1caf361c7..d13c9a826eef 100644
> --- a/drivers/gpu/nova-core/fb/hal/ga100.rs
> +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs
> @@ -9,8 +9,10 @@
>
> use crate::{
> driver::Bar0,
> - fb::hal::FbHal,
> - regs, //
> + fb::{
> + hal::FbHal,
> + regs, //
> + },
> };
>
> use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT;
> @@ -41,7 +43,7 @@ pub(super) fn write_sysmem_flush_page_ga100(bar: Bar0<'_>, addr: u64) {
> }
>
> pub(super) fn display_enabled_ga100(bar: Bar0<'_>) -> bool {
> - !bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
> + !bar.read(crate::regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
> .display_disabled()
> }
>
> diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-core/fb/hal/gb100.rs
> index 6e0eba101ca1..ec55ec3fc7e1 100644
> --- a/drivers/gpu/nova-core/fb/hal/gb100.rs
> +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs
> @@ -22,9 +22,11 @@
>
> use crate::{
> driver::Bar0,
> - fb::hal::FbHal,
> + fb::{
> + hal::FbHal,
> + regs, //
> + },
> num::usize_into_u32,
> - regs, //
> };
>
> struct Gb100;
> diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-core/fb/hal/gb202.rs
> index b78e0970f66d..69ba35d2ea08 100644
> --- a/drivers/gpu/nova-core/fb/hal/gb202.rs
> +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs
> @@ -12,8 +12,10 @@
>
> use crate::{
> driver::Bar0,
> - fb::hal::FbHal,
> - regs, //
> + fb::{
> + hal::FbHal,
> + regs, //
> + },
> };
>
> struct Gb202;
> diff --git a/drivers/gpu/nova-core/fb/hal/gh100.rs b/drivers/gpu/nova-core/fb/hal/gh100.rs
> index d39fe99537ed..2867ae058d0a 100644
> --- a/drivers/gpu/nova-core/fb/hal/gh100.rs
> +++ b/drivers/gpu/nova-core/fb/hal/gh100.rs
> @@ -10,8 +10,10 @@
>
> use crate::{
> driver::Bar0,
> - fb::hal::FbHal,
> - regs, //
> + fb::{
> + hal::FbHal,
> + regs, //
> + },
> };
>
> struct Gh100;
> diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs
> index f629e8e9d5d5..2ef04ccb550c 100644
> --- a/drivers/gpu/nova-core/fb/hal/tu102.rs
> +++ b/drivers/gpu/nova-core/fb/hal/tu102.rs
> @@ -9,8 +9,10 @@
>
> use crate::{
> driver::Bar0,
> - fb::hal::FbHal,
> - regs, //
> + fb::{
> + hal::FbHal, //
> + regs,
nit: `//` not on last line.
next prev parent reply other threads:[~2026-07-25 13:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 15:41 [PATCH 0/3] gpu: nova-core: Move PFB and PBUS register Antonin Malzieu Ridolfi via B4 Relay
2026-07-21 15:41 ` [PATCH 1/3] gpu: nova-core: Add function to query WPR2 range Antonin Malzieu Ridolfi via B4 Relay
2026-07-25 13:24 ` Alexandre Courbot
2026-07-27 15:07 ` Nanonej Dev
2026-07-21 15:41 ` [PATCH 2/3] gpu: nova-core: Move PFB registers definitions Antonin Malzieu Ridolfi via B4 Relay
2026-07-25 13:27 ` Alexandre Courbot [this message]
2026-07-27 15:17 ` Nanonej Dev
2026-07-21 15:41 ` [PATCH 3/3] gpu: nova-core: Move one PBUS register definition Antonin Malzieu Ridolfi via B4 Relay
2026-07-21 15:51 ` Nanonej Dev
2026-07-25 13:28 ` Alexandre Courbot
2026-07-25 13:30 ` Alexandre Courbot
2026-07-21 15:46 ` [PATCH 0/3] gpu: nova-core: Move PFB and PBUS register Nanonej Dev
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