From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58F483CB55B for ; Wed, 5 Aug 2026 18:43:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785955415; cv=none; b=YoKt7A2AtnNASJeympaXb5/F0iFXLQU+myUiVwP49y7jJxgf7ekKQaDvdMpsYO64SteZMXT79f/u83+r/+qDsQkPWlH4z3fM54gBHlsDrI72yFLFzgv95fXJZ+ekKVLI7alZpVE10SDPR6TgTFtkB/CsbyhrbL7Y9tPQF7kwXeE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785955415; c=relaxed/simple; bh=/L96/gtVu8w+HqtNVdkI17q939YFEY5Yc54ZVel4uOM=; h=Mime-Version:Content-Type:Date:Message-Id:Cc:Subject:From:To: References:In-Reply-To; b=OaDptMovd3X4p7uhU7x0GAxvCzW5W+Keoz0faHXHrHbEVy3iYHkZIDUW9ImSBtcdwDRodV8RQcFaYgRhrA/lmnL1s6pxxM92oMP5t7cxKspO1oX+XKk8G4Tkqml4w+jtCzUjw5dMzqcdEyltGPYP4yzyftgli50GBeYto8hF7bs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com; spf=pass smtp.mailfrom=cknow-tech.com; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b=fvnA+TH6; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b="fvnA+TH6" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow-tech.com; s=key1; t=1785955410; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=asjh1e4/12M1U47u0ygycydMMvDwaXnVjTSsGZZSUqA=; b=fvnA+TH6tPFnMy8EEtLfbmcwGCHaFIKnEjq/xXwB96nA0KfwmreSMXYBKBSESKTENGftEt t1eIchoAtsGfwfsYbDF1wKSrjhwkAY4qUA7zR8o+o+MLzPjD/+b30w+KXoyP24Bkym/Aot BbFhURaY1InqkfMQZgIVNHjMfVnZbamW8oRvMPzV1Ca/0KyXlhjdEA3wlcuje0xpfV1s9v G1MeObiamJcQpJgQZHwF8mf+0mHWQVe1qOA9kp9MEuJi4bjnlP+tPqW7vuRp2GDfBXGuFE AEUV2KleJIy+UemZQ6RD47XLE98bkjq0kjVz4KdSOB1naqIXR4E0m8+UFA4vZA== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 05 Aug 2026 20:43:27 +0200 Message-Id: Cc: "Oded Gabbay" , , , , "Jiaxing Hu" , "Heiko Stuebner" Subject: Re: [PATCH v2] accel/rocket: request the core clocks by name X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Diederik de Haas" To: "Igor Paunovic" , "Tomeu Vizoso" References: <20260729130743.128876-1-royalnet026@gmail.com> In-Reply-To: <20260729130743.128876-1-royalnet026@gmail.com> X-Migadu-Flow: FLOW_OUT Hi Igor, On Wed Jul 29, 2026 at 3:07 PM CEST, Igor Paunovic wrote: > rocket_core_init() hands core->clks to devm_clk_bulk_get() without ever > setting the .id members. The rocket_core array is allocated with > devm_kcalloc() in rocket_device_init(), and rocket_probe() only fills in > .rdev, .dev and .index, so all four clk_bulk_data entries are requested > with a NULL con_id (unlike core->resets, whose ids are set a few lines > above). > > clk_get(dev, NULL) ends up in of_clk_get_hw(np, 0, NULL), and > of_parse_clkspec() only consults "clock-names" when a name was passed, > so the index stays 0 for all four entries. Every entry therefore ends up > holding a handle to the *first* clock of the DT "clocks" property, i.e. > ACLK_NPUn. Nothing fails: probe succeeds and the driver believes it owns > four different clocks. > > The consequence is that rocket_device_runtime_resume() prepares and > enables the AXI clock four times, while hclk, pclk and - most > importantly - the NPU compute clock ("npu", SCMI_CLK_NPU on RK3588) are > never prepared or enabled by this driver at all. The NPU still works > only because the Rockchip power-domain driver sets GENPD_FLAG_PM_CLK and > its attach_dev() callback walks the device node with of_clk_get() and > adds every clock to the pm_clk list, so genpd happens to keep the > remaining clocks running. The bug is therefore latent today, but it > means the driver holds no reference to the clock that actually feeds the > NPU, which stands in the way of any future frequency scaling > (OPP/devfreq) work. > > Found on an Orange Pi 5 Plus (RK3588) by reading the live clock tree: > /sys/kernel/debug/clk/clk_summary shows four "fdab0000.npu" consumer > handles on aclk_npu0 (and likewise on aclk_npu1/aclk_npu2 for the other > two cores), while hclk_npu0, pclk_npu_root and scmi_clk_npu have no > "fdab0000.npu" consumer at all - their only consumers are the > "npu@fdab0000" handles created by the power-domain driver via > of_clk_get(). I have confirmed both the 'old' situation and the 'new' one on both my NanoPC-T6 LTS and NanoPC-T6 Plus (both RK3588), so feel free to add Tested-by: Diederik de Haas # NanoPC-T6 LTS, Nan= oPC-T6 Plus Cheers, Diederik > > Set the ids explicitly, in the order mandated by the binding > (Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml): > aclk, hclk, npu, pclk. After the change the driver holds one handle per > distinct clock and clk_bulk_prepare_enable() covers all four. > > Note that this is a user-visible tightening for out-of-tree DTs: the > old NULL-id requests resolved by index and succeeded no matter what > "clock-names" contained, while the named requests fail probe with > -ENOENT when one of the four names is missing. That is the right > outcome for in-tree users - the binding requires exactly these four > clock-names and rk3588-base.dtsi carries them on all three cores - but > a DT that relied on the permissive lookup goes from silently running on > the wrong clock handles to not probing at all, so record the change > here where git log will find it. > > Fixes: ed98261b4168 ("accel/rocket: Add a new driver for Rockchip's NPU") > Signed-off-by: Igor Paunovic > Reviewed-by: Jiaxing Hu > --- > v2: > - document that resolving by name is a behaviour change for DTs that > do not carry all four clock-names (Jiaxing Hu) > - collect Jiaxing's Reviewed-by > v1: https://lore.kernel.org/linux-rockchip/20260729092939.118779-1-royaln= et026@gmail.com/ > > The same four id assignments are board-tested on RK3576 (ROCK 4D) as > part of Jiaxing's RK3576 enablement series (v2 6/8), so the change has > been exercised on two SoCs between us. > > Verified on RK3588 (Orange Pi 5 Plus): after the change clk_summary > shows one consumer handle per clock instead of four handles on aclk, the > NPU still powers up and down cleanly through runtime PM, and a > MobileNetV1 inference run via the Teflon TFLite delegate produces > bit-identical output tensors to the unpatched driver. > > drivers/accel/rocket/rocket_core.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/ro= cket_core.c > index b3b2fa9..5dd260b 100644 > --- a/drivers/accel/rocket/rocket_core.c > +++ b/drivers/accel/rocket/rocket_core.c > @@ -28,6 +28,10 @@ int rocket_core_init(struct rocket_core *core) > if (err) > return dev_err_probe(dev, err, "failed to get resets for core %d\n", c= ore->index); > > + core->clks[0].id =3D "aclk"; > + core->clks[1].id =3D "hclk"; > + core->clks[2].id =3D "npu"; > + core->clks[3].id =3D "pclk"; > err =3D devm_clk_bulk_get(dev, ARRAY_SIZE(core->clks), core->clks); > if (err) > return dev_err_probe(dev, err, "failed to get clocks for core %d\n", c= ore->index); > > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip