From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD82D448D16 for ; Wed, 19 Aug 2026 09:53:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787133196; cv=none; b=Aomcdx7kSyqP2RGmaVtg3zx8BOCXQzA2Dtzu+/N1/O8f1evtQGlXuBeP8TfhzzSz6Jftm7mQ6FOOXFhbwGAq0zXDmocwn8g7Y+RgnGKJuzKyccpaQj5epSMDvdiKjWjychuFhLjlJbbQVy1DFYlbw16SciAGTFzcgsgMHunkEPo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787133196; c=relaxed/simple; bh=9GKWOZgXdxkeN8C/BGCypxKBZRGwJMWpWGLubdmg9T4=; h=Mime-Version:Content-Type:Date:Message-Id:To:From:Subject:Cc: References:In-Reply-To; b=ITRsESPNe4t4VQYOZIjBCuLriQK6lqqeqNG6sedY4nmtDu0aIJE7ODvtMyu3N+2aW5+XgPamZXjd+2IQTykgbyVr/KVx5WzLrAuqCO6MUl2WWf3GbWUpHtna5vziS63/KUymaK8e5k8vAGXoQZr0HXldQ9g9AkqFSODCFkjonNk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=yj5Es0c6; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="yj5Es0c6" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 4B98A4E412D0; Wed, 19 Aug 2026 09:53:01 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 06F715FF42; Wed, 19 Aug 2026 09:53:01 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 8819811C75589; Wed, 19 Aug 2026 11:52:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1787133175; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=SjXIs72QK5azP/b7Ud7PDBwyGS3GpesfQcCpzpeowVk=; b=yj5Es0c6gAhI+yYEgt42SUuug7t+mKeQKv9L60oQPIWBdboR8AoMGYbzHE64HmmzlY+JFE dvCqyXUjovopTi3wMZrFMbKn7Fld4/C3eBsI2qR6N6S8IaU0Dy+7Z40KHGjCataaeULq5l iSWVh6K4D+/+r+yRE46/jmaIQU+JRHUBI/yeYdlNxh8vOhxtlV4Q9nWGLXlWekzatOJXYY I1EyKc3tBGj2is4XrClsXjxygCk89dPf91WhGFvLAPu02wJLz+1Mt0cmPRH+t5gmlA36Hz 40l43m3SqWEW8J/jxzfanB69IEvADfmF/u1WIKyQHhyuvZMw6xqouRgyHA9zQA== Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 19 Aug 2026 11:52:44 +0200 Message-Id: To: "Svyatoslav Ryhel" , "Andrzej Hajda" , "Neil Armstrong" , "Robert Foss" , "Laurent Pinchart" , "Jonas Karlman" , "Jernej Skrabec" , "Luca Ceresoli" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "David Airlie" , "Simona Vetter" From: "Luca Ceresoli" Subject: Re: [PATCH v2 1/1] gpu/drm: bridge: tc358768: Add delay after PLL setup Cc: , X-Mailer: aerc 0.22.0 References: <20260625082507.57703-1-clamor95@gmail.com> <20260625082507.57703-2-clamor95@gmail.com> In-Reply-To: <20260625082507.57703-2-clamor95@gmail.com> X-Last-TLS-Session-Version: TLSv1.3 Hello Svyatoslav, On Thu Jun 25, 2026 at 10:25 AM CEST, Svyatoslav Ryhel wrote: > After tc358768_setup_pll() enables PLL_CKEN and the lock indicator comes > up, the DSI register sequence runs near immediately. On TF700T this Do you refer to the Asus Transformer Pad TF700T here? Please add the full name of the device. > results in the bridge claiming PLL lock but producing no DSI video output= : > the panel powers up, the backlight comes on, but the framebuffer is never > scanned out. > > Insert a small settling delay between PLL setup and the rest of the > attach. > > Suggested-by: Michele Brocco > Tested-by: Michele Brocco # TF700T > Signed-off-by: Svyatoslav Ryhel > --- > drivers/gpu/drm/bridge/tc358768.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/t= c358768.c > index 0f2820b37302..ea358c8da0e9 100644 > --- a/drivers/gpu/drm/bridge/tc358768.c > +++ b/drivers/gpu/drm/bridge/tc358768.c > @@ -824,6 +824,9 @@ static void tc358768_bridge_atomic_pre_enable(struct = drm_bridge *bridge, > return; > } > > + /* Allow the PLL to settle */ > + mdelay(20); Why 20 ms, and not another amount? Is it backed by some datasheet? Or just "it's what fixed my usecase"? The extra delay is a panel requirement maybe, and definitely specific to the specific hardware pipeline of the TF700T. Would it make sense to add a DT property so only hardware needing a delay can add it, and add as much as needed? Luca -- Luca Ceresoli, Bootlin Embedded Linux and Kernel engineering https://bootlin.com