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Sun, 06 Sep 2026 19:20:43 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 6232298470301250172 EX-QQ-RecipientCnt: 19 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Type: multipart/signed; boundary=536c7c79d9464b992ad1d7b5be05ae3641e4b875bba8fe2b43dc9e787550; micalg=pgp-sha512; protocol="application/pgp-signature" Date: Sun, 06 Sep 2026 19:20:40 +0800 Message-Id: From: "Troy Mitchell" To: "Yixun Lan" , "Troy Mitchell" Cc: "Aurelien Jarno" , "Michael Turquette" , "Inochi Amaoto" , "Alex Elder" , "Haylen Chu" , , "Stephen Boyd" , "Brian Masney" , "Jerome Brunet" , "Paul Walmsley" , "Palmer Dabbelt" , "Albert Ou" , "Alexandre Ghiti" , , , , Subject: Re: [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables Content-Transfer-Encoding: quoted-printable X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260903-k3-pll5-pll8-1800mhz-v4-1-afafd9cb47d9@linux.spacemit.com> <20260905220746-GKC53903@kernel.org> In-Reply-To: <20260905220746-GKC53903@kernel.org> X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpsz:linux.spacemit.com:qybglogicsvrgz:qybglogicsvrgz3a-0 X-QQ-XMAILINFO: NGf6Juddf2av1Bk8NfLKPcxvsFIALwEmDxNU0SXF7DhV2BjuVFczEfwY htGBs9UrUW2g01HBaf3PYHQEPBbEAFKJMkgPqfklaw14hJa146zEVYgNoVAu5pi1+y/vm0+ sknWUEKuL7RRn9vBURBozE/F8Ix80dIx73+UskZL6KdM9L/TlmXtpGNGVAr++cRKTi6DZxd KYsfletsNI0co3Tr1Gsm7CDG6vZQlDr5Mib3V2io14GwwOHywbrg4Yv3Ajq2NxnQApc7cin 7frk8Zvem3GJ+tZ8vXTcw1W/AESr7tkxMys4mAhWl3NhsXjLMigz+ewR5wBPFqpuxRFT3bg Wy1H08tbESosANSaIpplzCEsHQJiL9zugfvwimN1JuHPLg/VPiB8A5E1KmyRGwv4oL5gydy +YyAqTBzB5fu4CaOAOGtcx5IQ983rxUHkUU+T7Cs4HYhpVCbFlDHNxmZB6kCuUfJNO/fp+i NV6hnRxQ+nZqrOUOcc8ANvoKjFXCKnvaTKdP1CNc2WjfxttRC20WBjnVYBaSf/DGp3Zfw+F M13LTFGeymqG+/Z/OfW3jP1V5VntKUK/uIY0xLZGvJ3gD8Enagj1RHVDUHBjsipfJVmKNee ABv3lC/vlgW25+PDX2iZYbUqPw/2z2DsL8MGgWmgDyUBYCI0fN0e/JGxLAXQGKdwDD1/PYk J2a6/WBgbjjIyIUBKmo0XUsR7E5mgnNebKiLjIDFlTSMzmTlcsr62UCZXzub3Cr76xb0vfb aDDrZjhWd0bmjeouQscdj6img/k9w0+N9/hS8aNNNlSbo8GABhIjM3vQrblXolEnON+VXtJ g4kdifuEVS9pYHuuwgHD0+q6BMU93Lj7uo4p16delEx4w0IHw5yWp1wVqayi26t1aP5sHXJ BZa09ftphjJtRC882MTF3WVYlakJW6ONMaZNeqB5f8eiDfh2dis9w9cXfc/P7guY41IgmHO B1uel3MGhme/iyz3Pjpbw4miiNktGwmFv8Lk3nfClmxI0QA8PsWrRmaUkXYZf9HJjwPRie9 L4ljc/liPlIbUPxxH93QDtULvq9p+2r1ctQI7/XIEFs/2BBOmeoXiQ9kEyWVKhpkBaUpIU9 Bt+hahoSmjCcEEMTEg+37UFzSRBjrz9mw8KSophvK7m2Moop6xGYrOmRoKYCEDvKg== X-QQ-XMRINFO: Nq+8W0+stu50tPAe92KXseR0ZZmBTk3gLg== X-QQ-RECHKSPAM: 0 --536c7c79d9464b992ad1d7b5be05ae3641e4b875bba8fe2b43dc9e787550 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi Yixun, Aurelien On Sun Sep 6, 2026 at 6:07 AM +08, Yixun Lan wrote: > Hi Aurelien, Troy, > > On 11:24 Fri 04 Sep , Troy Mitchell wrote: >> Hi Aurelien, >>=20 >> On Fri Sep 4, 2026 at 1:27 AM +08, Aurelien Jarno wrote: >> > Hi Troy, >> > > .. >> >> drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++= ++++++++++ >> >> 1 file changed, 96 insertions(+) >> > >> > Thanks for the patch, it makes sense to add all the values, to support= =20 >> > future firmware changes. The values match the ones in the vendor kerne= l. >> I forgot that you had a similar patch as well.. >>=20 >> > >> >> diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu= -k3.c >> >> index 92b930d5ff30..950bf531c734 100644 >> >> --- a/drivers/clk/spacemit/ccu-k3.c >> >> +++ b/drivers/clk/spacemit/ccu-k3.c >> >> @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tb= l[] =3D { >> >> CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), >> >> }; >> >> =20 >> >> +/* Keep the firmware default as the first entry. */ >> >> static const struct ccu_pll_rate_tbl pll3_rate_tbl[] =3D { >> >> + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), >> > >> > Is it really necessary to put this entry first? I guess it's the curre= nt=20 >> > default frequency, but we have seen it can evolve. From my tests, the= =20 >> > driver seems to just keep the value configured by the firmware=20 >> > independently from the table order, so I am not sure it's necessary. > > I agree with Aurelien here, the default frequency isn't a solid stable se= ttings, > which it may changes in the future > >> I think keeping it first is necessary. If the current register settings = do >> not match any entry in the table, ccu_plla_init() falls back to the firs= t > > Isn't it a bug if all frequencies added still couldn't cover all settings= ? > I'd simply suggest to bail out and yell loudly if there is a mismatch > > I just don't like putting specific frequency at first one as default, > this logic is kind of fragile and tend to fail easily.. I checked the Rockchip PLL driver. The RK3036, RK3066 and RK3399 implementations calculate the current rate directly from the hardware register parameters. If that rate is absent from the rate table, their PLL init callbacks return without reprogramming the PLL. With ROCKCHIP_PLL_SYNC_RATE enabled, they only synchronize the parameters when the current rate matches a table entry but the register parameters differ from those in that entry. This approach seems preferable to me. Would it make sense to sort the rate tables by frequency in the next revision, and follow up with a separate series to calculate the current rate from the registers and preserve configurations whose rates are absent from the table, as Rockchip does? > >> entry: >>=20 >>=20 >> ccu_plla_update_param(pll, &pll->config.rate_tbl[0]); >>=20 --=20 Troy Mitchell --536c7c79d9464b992ad1d7b5be05ae3641e4b875bba8fe2b43dc9e787550 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iIMEABYKACsWIQSL4Ay2cExaPXAQcU2YCe+A+TM0LwUCap1MiA0caUB0cm95LXku b3JnAAoJEJgJ74D5MzQv+TcBAKuYgm3NzSdu2AewDdZD9GRhXTKU8Kg7xc4yVrlo nVfcAQC2ZNkxsjsFJBZyiwSwQYWdYZq+bsxMX1yf4dEkWAOCAg== =J7rf -----END PGP SIGNATURE----- --536c7c79d9464b992ad1d7b5be05ae3641e4b875bba8fe2b43dc9e787550--