From: "Michael Walle" <mwalle@kernel.org>
To: "Nuno Sá" <nuno.sa@analog.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: "Pratyush Yadav" <pratyush@kernel.org>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
"Miquel Raynal" <miquel.raynal@bootlin.com>,
"Richard Weinberger" <richard@nod.at>,
"Vignesh Raghavendra" <vigneshr@ti.com>
Subject: Re: [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g
Date: Mon, 14 Sep 2026 08:28:25 +0200 [thread overview]
Message-ID: <DLETRRVRUWEP.1VU1EHARD3MSH@kernel.org> (raw)
In-Reply-To: <20260911-mtd-spi-nor-new-issi-chip-v1-2-c54615f8c30f@analog.com>
Hi,
On Fri Sep 11, 2026 at 5:36 PM CEST, Nuno Sá wrote:
> Add support for the ISSI IS25WX01G, a 1 Gbit octal NOR flash. The part
> is fully described by SFDP, so only the flash ID and two BFPT fixups are
> needed.
Adding a new flash involves minimum testing and an SFDP dump, see
[1].
Also please keep the following Link: tag in your next version:
Link: https://www.issi.com/WW/pdf/25LX-WX01GB.pdf
> The flash has no Status Register 2 and does not implement the 35h Read
> Configuration Register command, so the default assumption of a 16-bit
> Write Status command does not hold. Additionally, its BFPT Quad Enable
> Requirement field carries a reserved value, which makes
> spi_nor_parse_bfpt() keep the manufacturer default quad enable method;
> clear it, since this is an octal-only part with no quad mode at all.
>
> Signed-off-by: Nuno Sá <nuno.sa@analog.com>
> ---
> drivers/mtd/spi-nor/issi.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c
> index 2f057d731df2..aac9d19b90fc 100644
> --- a/drivers/mtd/spi-nor/issi.c
> +++ b/drivers/mtd/spi-nor/issi.c
> @@ -29,6 +29,29 @@ static const struct spi_nor_fixups is25lp256_fixups = {
> .post_bfpt = is25lp256_post_bfpt_fixups,
> };
>
> +static int is25wx01g_post_bfpt_fixups(struct spi_nor *nor,
> + const struct sfdp_parameter_header *bfpt_header,
> + const struct sfdp_bfpt *bfpt)
> +{
> + /*
> + * There is no Status Register 2 and no 35h command. And WRITE STATUS
> + * REGISTER takes a single data byte.
> + */
> + nor->flags &= ~SNOR_F_HAS_16BIT_SR;
> +
> + /*
> + * The BFPT Quad Enable Requirement field is set to a reserved value, so
> + * spi_nor_parse_bfpt() leaves the quad enable method at its default.
> + * Make sure we disable it as there is no quad mode anyway.
> + */
> + nor->params->quad_enable = NULL;
> + return 0;
> +}
> +
> +static const struct spi_nor_fixups is25wx01g_fixups = {
> + .post_bfpt = is25wx01g_post_bfpt_fixups,
> +};
> +
> static int pm25lv_nor_late_init(struct spi_nor *nor)
> {
> struct spi_nor_erase_map *map = &nor->params->erase_map;
> @@ -120,6 +143,10 @@ static const struct flash_info issi_nor_parts[] = {
> .id = SNOR_ID(0x9d, 0x70, 0x19),
> .name = "is25wp256",
> .flags = SPI_NOR_QUAD_PP,
> + }, {
> + .id = SNOR_ID(0x9d, 0x5b, 0x1b),
> + .name = "is25wx01g",
No .name please.
-michael
[1] https://docs.kernel.org/driver-api/mtd/spi-nor.html
> + .fixups = &is25wx01g_fixups,
> }
> };
>
next prev parent reply other threads:[~2026-09-14 6:37 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 15:36 [PATCH 0/2] mtd: spi-nor: issi: add support for the IS25WX01G octal flash Nuno Sá
2026-09-11 15:36 ` [PATCH 1/2] mtd: spi-nor: sfdp: get the 1-1-8 and 1-8-8 page programs from 4BAIT Nuno Sá
2026-09-11 15:36 ` [PATCH 2/2] mtd: spi-nor: issi: Add support for is25wx01g Nuno Sá
2026-09-11 15:44 ` sashiko-bot
2026-09-11 16:09 ` Nuno Sá
2026-09-14 6:28 ` Michael Walle [this message]
2026-09-14 8:20 ` Nuno Sá
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