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Tue, 22 Sep 2026 16:42:48 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 23 Sep 2026 00:42:48 +0100 Message-Id: Cc: , , , , , , , "Konrad Dybcio" Subject: Re: [PATCH v3 1/5] clk: qcom: fix SM6115 lpasscc register offset From: "Alexey Klimov" To: "Srinivas Kandagatla" , , , , , , , X-Mailer: aerc 0.21.0 References: <3a4e8d1115a46c45cb34193b6ceeb02891fdf716.1790114902.git.srinivas.kandagatla@oss.qualcomm.com> In-Reply-To: <3a4e8d1115a46c45cb34193b6ceeb02891fdf716.1790114902.git.srinivas.kandagatla@oss.qualcomm.com> On Tue Sep 22, 2026 at 11:11 PM BST, Srinivas Kandagatla wrote: > For some reason we ended with incorrect register offset for soundwire tx > controller reset and the regmap register max was also incorrect it was > 0x1000 instead of 0x12000 which is full register range for this IP. > > This was somehow compenseated in DT reg property which got it working so > far. > > Fix this by correcting the actual offset and max registers as per SoC > documentation. > > Fixes: b076b995e225 ("clk: qcom: Add SM6115 LPASSCC") > Cc: Konrad Dybcio > Signed-off-by: Srinivas Kandagatla Reviewed-by: Alexey Klimov