Re: [PATCH v3 05/33] gpu: nova-core: regs: add msgq v2 BAR0 register declarations

["Alexandre Courbot" <acourbot@nvidia.com>]

On Fri Sep 18, 2026 at 10:06 AM JST, John Hubbard wrote:
> Msgq is the pair of ring buffers in shared memory through which the
> driver and GSP-RM communicate. The command queue carries commands from
> the driver to GSP-RM, and the message queue carries messages from GSP-RM
> to the driver. Each ring buffer has a write pointer and a read pointer.
>
> Msgq v0, which the r570 firmware uses, keeps both pointers of each ring
> buffer in that ring buffer's header, in shared memory. Msgq v2, which
> the r000 firmware uses, keeps the four pointers, two per ring buffer, in
> four BAR0 registers instead:
>
>     NV_PGSP_QUEUE_HEAD    command queue write pointer
>     NV_PGSP_QUEUE_TAIL    command queue read pointer
>     NV_PGSP_MSGQ_HEAD     message queue write pointer
>     NV_PGSP_MSGQ_TAIL     message queue read pointer
>
> The GSP numbers its queues 0 through 7, and each numbered queue is one
> such pair of ring buffers with its own four pointer registers, so the
> hardware has 32 pointer registers in all. Nova-core uses queue 0 only.
>
> A write to NV_PGSP_QUEUE_HEAD also interrupts the GSP. Msgq v0 uses that
> write as the doorbell, so nova-core already declares NV_PGSP_QUEUE_HEAD.
>
> Declare the other three, NV_PGSP_QUEUE_TAIL, NV_PGSP_MSGQ_HEAD and
> NV_PGSP_MSGQ_TAIL, each as a scalar at its queue 0 offset rather than as
> an array of eight.

I understand that at the moment we are only using the first of these
registers (and `NV_PGSP_QUEUE_HEAD` was already declared that way), but
technically they are arrays of 8 - let's take the opportunity to declare
them accurately and stop deriving from the hardware definition.