On Mon Sep 21, 2026 at 4:03 PM +08, Manivannan Sadhasivam wrote:
> On Mon, Sep 21, 2026 at 01:55:42PM +0800, Encrow Thorne wrote:
>
> [...]
>
>> Hi Bruno,
>> 
>> The issue was caused by a missing hardware configuration in the K1 PCIe
>> initialization.
>> 
>> The PMU PCIE_CONTROL_LOGIC register contains an IGNORE_PERSTN bit (BIT(2)).
>> The hardware manual describes it as follows:
>> 
>> “When set to 1, the PCIe controller and PHY ignore the PERSTN signal from
>> the link partner in both RC and EP modes.”
>> 
>> This bit was not configured during RC initialization. As a result, the
>> controller and PHY could still be affected by the PERSTN input during the
>> early DBI accesses. With the Intel I225-V installed, the first DBI access
>> could remain pending and hang the CPU.
>> 
>
> What does this 'PERSTN' bit controls? PERST# or something else? PERST# is
> controlled only by the Root Complex btw. Also, why does this missing register
> configuration only affecting Intel I225-V endpoint and not others?
Encrow has already posted a patch here [1] and explained the reasoning; it seems to
depend on the device's behavior.

Link: https://lore.kernel.org/all/20260924-spacemit-k1-pcie-fix-v1-1-002b5c1ba9fc@linux.spacemit.com/ [1]


-- 
Troy Mitchell