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Date: Wed, 30 Sep 2026 22:34:27 +0200
Message-Id: <DLSXS9MO4YW5.2YLITM1OJ7P0P@kernel.org>
Subject: Re: [PATCH v10 1/1] rust: pci: add extended capability and SR-IOV
 support
Cc: <rust-for-linux@vger.kernel.org>, <linux-pci@vger.kernel.org>,
 <linux-kernel@vger.kernel.org>, <aliceryhl@google.com>,
 <bhelgaas@google.com>, <kwilczynski@kernel.org>, <ojeda@kernel.org>,
 <boqun@kernel.org>, <gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
 <lossin@kernel.org>, <a.hindborg@kernel.org>, <tmgross@umich.edu>,
 <markus.probst@posteo.de>, <cjia@nvidia.com>, <smitra@nvidia.com>,
 <ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
 <targupta@nvidia.com>, <kjaju@nvidia.com>, <alkumar@nvidia.com>,
 <acourbot@nvidia.com>, <jhubbard@nvidia.com>, <zhiwang@kernel.org>,
 =?utf-8?q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>
To: "Zhi Wang" <zhiw@nvidia.com>
From: "Danilo Krummrich" <dakr@kernel.org>
References: <20260906060404.3336193-1-zhiw@nvidia.com>
 <20260906060404.3336193-2-zhiw@nvidia.com>
In-Reply-To: <20260906060404.3336193-2-zhiw@nvidia.com>

On Sun Sep 6, 2026 at 8:04 AM CEST, Zhi Wang wrote:
> +    pub fn vf_bars(&self) -> Result<impl Iterator<Item =3D ExtSriovVfBar=
>> {
> +        let slots: [u32; NUM_VF_BARS] =3D
> +            core::array::from_fn(|slot| crate::io_read!(*self, .vf_bar[p=
anic: slot]));
> +        let mut slots =3D slots.into_iter();
> +        let mut bars =3D [None; NUM_VF_BARS];
> +        let mut count =3D 0;
> +
> +        let mut decode =3D || {
> +            while let Some(low) =3D slots.next().map(BarLow::from) {
> +                // SR-IOV VF BARs describe memory-space apertures; an I/=
O-space encoding is not
> +                // valid for these registers.
> +                if low.io_space() {
> +                    return Err(EINVAL);
> +                }
> +
> +                let low_address =3D u64::from(low.address()) << BarLow::=
ADDRESS_SHIFT;
> +                let bar =3D match low.memory_type()? {
> +                    BarMemoryType::Bits64 =3D> ExtSriovVfBar {
> +                        address: (u64::from(slots.next().ok_or(EINVAL)?)=
 << 32) | low_address,
> +                        is_64bit: true,
> +                    },
> +                    BarMemoryType::Bits32 =3D> ExtSriovVfBar {
> +                        address: low_address,
> +                        is_64bit: false,
> +                    },
> +                };
> +
> +                bars[count] =3D Some(bar);
> +                count +=3D 1;
> +            }
> +
> +            Ok(())
> +        };
> +
> +        decode().inspect_err(|_| {
> +            dev_err!(self.pdev, "invalid VF BAR encoding in SR-IOV capab=
ility\n");
> +        })?;
> +        Ok(bars.into_iter().flatten())
> +    }

I don't mind too much, but can you please remind me why we decode the VF BA=
R
registers and can't use the PCI core's VF resource information instead?

(I gave it a very quick try and using pci_bus_address() and pci_resource_fl=
ags()
actually turned out worse, but that could be me spending less than 5 minute=
s on
it. :)